IEICE Technical Committee

[Date]2023-11-16
[Paper #]VLD2023-43,ICD2023-51,DC2023-50,RECONF2023-46

Computation-in-Memory Generating Approximate Random Weight for Neuromorphic Computing

Naoko Misawa(Univ. of Tokyo), Shunsuke Koshino(Univ. of Tokyo), Chihiro Matsui(Univ. of Tokyo), Ken Takeuchi(Univ. of Tokyo),

[Date]2023-11-16
[Paper #]VLD2023-46,ICD2023-54,DC2023-53,RECONF2023-49

Quantization Method of Computation-in-Memory for 1/10 Memory Size Vision Transformer

Naoko Misawa(Univ. of Tokyo), Ryuhei Yamaguchi(Univ. of Tokyo), Ayumu Yamada(Univ. of Tokyo), Chihiro Matsui(Univ. of Tokyo), Ken Takeuchi(Univ. of Tokyo),

[Date]2023-11-16
[Paper #]VLD2023-47,ICD2023-55,DC2023-54,RECONF2023-50

Analysis and Improvement of the Parallel Implementation of Linear FSMs for Reducing the Latency in Stochastic Computing

Kota Okahara(Hiroshima City Univ.), Hideyuki Ichihara(Hiroshima City Univ.), Tomoo Inoue(Hiroshima City Univ.),

[Date]2023-11-16
[Paper #]VLD2023-50,ICD2023-58,DC2023-57,RECONF2023-53

A Proposal for Acceleration of FPGA-based Linear Equation Solver using Speculative Execution System

Naoki Kakine(HCU), Shuto Yuya(HCU), Atsushi Kubota(HCU), Tetsuo Hironaka(HCU),

[Date]2023-11-16
[Paper #]VLD2023-53,ICD2023-61,DC2023-60,RECONF2023-56

Implementation Evaluation of a Memorism Pattern Matching Accelerator on FPGA

Shion Honda(Ehime Univ.), Tatsuya Nishikawa(Ehime Univ.), Xihong Zhou(Ehime Univ.), Senling Wang(Ehime Univ.), Hiroshi Kai(Ehime Univ.), Yoshinobu Higami(Ehime Univ.), Hiroshi Takahashi(Ehime Univ.), Katsumi Inoue(AOT),

[Date]2023-11-16
[Paper #]VLD2023-61,ICD2023-69,DC2023-68,RECONF2023-64

Implementation of Neural Networks in Memory-based Reconfigurable Processor

Kenta Sasagawa(Ehime Univ.), Tatsuya Nishikawa(Ehime Univ.), Xihong Zhou(Ehime Univ.), Senling Wang(Ehime Univ.), Hiroshi Kai(Ehime Univ.), Hiroshi Takahashi(Ehime Univ.),

[Date]2023-11-16
[Paper #]VLD2023-51,ICD2023-59,DC2023-58,RECONF2023-54

Calculation of Isomorphic/Similar Topology using Graph Theory

Yuto Moriguchi(KIT), Nobukazu Takai(KIT),

[Date]2023-11-16
[Paper #]VLD2023-55,ICD2023-63,DC2023-62,RECONF2023-58

Proposed power supply layout for RF circuits with a power panel containing MOM capacitors, bias control lines, and electrostatic protection diodes

Shunto Nishiura(Hiroshima Univ.), Satoshi Tanaka(Hiroshima Univ.), Takeshi Yoshida(Hiroshima Univ.), Minoru Fujishima(Hiroshima Univ.),

[Date]2023-11-16
[Paper #]VLD2023-58,ICD2023-66,DC2023-65,RECONF2023-61

Hardware obfuscation method using Obfuscator-LLVM and Bambu

Mikiya Ogura(Toyohashi Univ. Tech.), Shuichi Ichikawa(Toyohashi Univ. Tech.),

[Date]2023-11-16
[Paper #]VLD2023-54,ICD2023-62,DC2023-61,RECONF2023-57

レイアウト起因LSI欠陥検出における欠陥モデルとデータ拡張手法の検討

Takumi Sugioka(Tokyo Metoropolitan Univ.), Yosikazu Nagamura(Tokyo Metoropolitan Univ.), Masayuki Arai(Nihon Univ.), Satoshi Fukumoto(Tokyo Metoropolitan Univ.),

[Date]2023-11-16
[Paper #]VLD2023-62,ICD2023-70,DC2023-69,RECONF2023-65

A multi bit PWM-DAC with calibration for quantum computing

Shunsuke Akahosh(KIT), Nobukazu Takai(KIT),

[Date]2023-11-16
[Paper #]VLD2023-56,ICD2023-64,DC2023-63,RECONF2023-59

Wearable Perspiration Meter System with 0.18 ?m BCD Process and Experimental Investigations for High Precision

Shunsaku Mineo(Shinshu Univ.), Ayumu Yamamoto(Shinshu Univ.), Shin-Ichiro Kuroki(Hiroshima Univ.), Hideya Momose(SKINOS), Koh Johguchi(Shinshu Univ.),

[Date]2023-11-16
[Paper #]VLD2023-57,ICD2023-65,DC2023-64,RECONF2023-60

Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory

Sae Goto(Okayama Univ.), Minoru Watanabe(Okayama Univ.), Akifumi Ogiwara(Kobe City College of Technology), Nobuya Watanabe(Okayama Univ.),

[Date]2023-11-17
[Paper #]VLD2023-71,ICD2023-79,DC2023-78,RECONF2023-74

Study on the Application of Compressed Sensing Utilizing Random Undersampling to Heart Sound Measurement System

Tomoya Yamamoto(Osaka Univ), Daisuke Kanemoto(Osaka Univ), Hirotada Masuda(Osaka Univ), Tetsuya Hirose(Osaka Univ),

[Date]2023-11-17
[Paper #]VLD2023-66,ICD2023-74,DC2023-73,RECONF2023-69

Configuration Data Compression for SLM Fine-grained Reconfigurable Logic

Souhei Takagi(Keio Univ), Takuya Kozima(Keio Univ), Hideharu Amano(Keio Univ), Morihiro Kuga(Kumamoto Univ), Masahiro Iida(Kumamoto Univ),

[Date]2023-11-17
[Paper #]VLD2023-72,ICD2023-80,DC2023-79,RECONF2023-75

An Improved Routing Method by SAT for Set-Pair Routing Problem

Koki Nagakura(TUAT), Kunihiro Fujiyoshi(TUAT),

[Date]2023-11-17
[Paper #]VLD2023-77,ICD2023-85,DC2023-84,RECONF2023-80

Maximum operating clock frequency evaluation of Mono Instruction Set Computers on an optically reconfigurable gate array VLSI

Soma Imai(Okayama Univ.), Minoru Watanabe(Okayama Univ.), Nobuya Watanabe(Okayama Univ.),

[Date]2023-11-17
[Paper #]VLD2023-74,ICD2023-82,DC2023-81,RECONF2023-77

A comparator with variable offset voltage variation by controlling differential pair’s currents

Taira Sakaguchi(Tokyo Denki Univ.), Satoshi Komatsu(Tokyo Denki Univ.),

[Date]2023-11-17
[Paper #]VLD2023-67,ICD2023-75,DC2023-74,RECONF2023-70

A wafer-scale VLSI realization using optical reconfiguration architecture

Atsushi Takata(Okayama Univ.), Minoru Watanabe(Okayama Univ.), Nobuya Watanabe(Okayama Univ.),

[Date]2023-11-17
[Paper #]VLD2023-70,ICD2023-78,DC2023-77,RECONF2023-73