Information and Systems-Dependable Computing(Date:2022/11/28)

Presentation
FPGA Implementation of Learned Image Compression

Heming Sun(Waseda U),  Qingyang Yi(UTokyo),  Jiro Katto(Waseda U),  Masahiro Fujita(UTokyo),  

[Date]2022-11-30
[Paper #]VLD2022-53,ICD2022-70,DC2022-69,RECONF2022-76
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter

Shoma Ito(Tokai Univ.),  Daishi Nishiguchi(Tokai Univ.),  Masaaki Fukuhara(Tokai Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-45,ICD2022-62,DC2022-61,RECONF2022-68
Deep Learning-based Hierarchical Object Detection System for High-Resolution Images

Yusei Horikawa(Nihon Univ.),  Makoto Sugaya(Nihon Univ.),  Renpei Yoshida(Nihon Univ.),  Kazuma Mashiko(Nihon Univ.),  Tetsuya Matsumura(Nihon Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-44,ICD2022-61,DC2022-60,RECONF2022-67
Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples

Yuta Fukuda(Ritsumeikan Univ.),  Kota Yoshida(Ritsumeikan Univ.),  Takeshi Fujino(Ritsumeikan Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-51,ICD2022-68,DC2022-67,RECONF2022-74
NA

Kota Hisafuru(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-54,ICD2022-71,DC2022-70,RECONF2022-77
Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops

Daiki Yokoyama(SIT),  Kimiyoshi Usami(SIT),  Aika Kamei(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-39,ICD2022-56,DC2022-55,RECONF2022-62
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects

Eisuke Ohama(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-46,ICD2022-63,DC2022-62,RECONF2022-69
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise

Ryoga Iwashita(UTokyo),  Zule Xu(UTokyo),  Masaru Osada(UTokyo),  Ryoya Shibata(UTokyo),  Yo Kumano(UTokyo),  Tetsuya Iizuka(UTokyo),  

[Date]2022-11-30
[Paper #]VLD2022-43,ICD2022-60,DC2022-59,RECONF2022-66
A contact angle estimation method using two coplanar capacitive sensors of different sizes

Tsubasa Furuta(USP),  Akira Tsuchiya(USP),  Toshiyuki Inoue(USP),  Keiji Kishine(USP),  

[Date]2022-11-30
[Paper #]VLD2022-42,ICD2022-59,DC2022-58,RECONF2022-65
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC

Keigo Takami(Tokushima Univ. Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-47,ICD2022-64,DC2022-63,RECONF2022-70
FPGA Implementation and Area Evaluation of JTAG Access Mechanism Using Lightweight One-Time Password Authentication Scheme

Hisashi Okamoto(Ehime Univ),  Jun Ma(Ehime Univ),  Senling Wang(Ehime Univ),  Hiroshi Kai(Ehime Univ),  Hiroshi Takahashi(Ehime Univ),  Akihiro Shimizu(Kochi Univ. of Technology),  

[Date]2022-11-30
[Paper #]VLD2022-48,ICD2022-65,DC2022-64,RECONF2022-71
Development of 65nm-Cryo-CMOS Circuit Design Library

Toshitsugu Sakamoto(NBS),  Makoto Miyamura(NBS),  Kazunori Funahashi(NBS),  Koichiro Okamoto(NBS),  Munehiro Tada(NBS),  Takahisa Tanaka(Tokyo Univ.),  Ken Uchida(Tokyo Univ.),  Hiroki Ishikuro(Keio Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-38,ICD2022-55,DC2022-54,RECONF2022-61
Mask Optimization Using Voronoi Partition and Iterative Improvement

Naoki Nonaka(Univ. of Aizu),  Yukihide Kohira(Univ. of Aizu),  Atsushi Takahashi(Tokyo Tech),  Chikaaki Kodama(KIOXIA),  

[Date]2022-11-30
[Paper #]VLD2022-41,ICD2022-58,DC2022-57,RECONF2022-64
A fast SRAF optimization used LUT based intensity estimation

Sota Saito(Tokyo Tech),  Atsushi Takahashi(Tokyo Tech),  

[Date]2022-11-30
[Paper #]VLD2022-40,ICD2022-57,DC2022-56,RECONF2022-63
Implementation of stereo matching with Kria SOM toward precise field crop height measurement

Ryo Nakagawa(Univ. of Tsukuba),  Yoshiki Yamaguchi(Univ. of Tsukuba),  Iman Firmansyah(BRIN),  

[Date]2022-11-30
[Paper #]VLD2022-52,ICD2022-69,DC2022-68,RECONF2022-75
高速シリアルトランシーバ向けの汎用型ビットエラーテスタの検討

Hisayuki Tamashiro(Ryukyu Univ),  Yasunori Osana(Ryukyu Univ),  

[Date]2022-11-30
[Paper #]VLD2022-50,ICD2022-67,DC2022-66,RECONF2022-73
Error detection and countermeasures for computers inserted with hardware Trojan

Takuro Kasai(Hirosaki Univ.),  Masashi Imai(Hirosaki Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-55,ICD2022-72,DC2022-71,RECONF2022-78
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