Information and Systems-Dependable Computing(Date:2016/11/28)

Presentation
Accurate Lithography Simulation Model based on Deep Learning

Yuki Watanabe(Toshiba),  Tetsuaki Matsunawa(Toshiba),  Taiki Kimura(Toshiba),  Shigeki Nojima(Toshiba),  

[Date]2016-11-29
[Paper #]VLD2016-56,DC2016-50
[Invited Talk] Ultra-large-scale ultra-high-speed image display technology and applications

Hidemichi Kawase(Kamiens),  

[Date]2016-11-29
[Paper #]CPM2016-80,ICD2016-41,IE2016-75
Optimal configuration design of SCM and MLC/TLC NAND flash memory in semiconductor storage system

Chihiro Matsui(Chuo Univ.),  Yusuke Yamaga(Chuo Univ.),  Yusuke Sugiyama(Chuo Univ.),  Ken Takeuchi(Chuo Univ.),  

[Date]2016-11-29
[Paper #]CPM2016-77,ICD2016-38,IE2016-72
Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm

Toshiki Higashi(Ritsumeikan Univ.),  Hiroyuki Ochi(Ritsumeikan Univ.),  

[Date]2016-11-29
[Paper #]RECONF2016-45
Development of power estimation tool for three dimensional FPGA

Masato Ikebe(Kumamoto Univ.),  Qian Zhao(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2016-11-29
[Paper #]RECONF2016-46
Length Difference Minimization with Exchanging Pin Pair for Set Pair Routing Problem

Shutaro Hara(TUAT),  Kunihiro Fujiyoshi(TUAT),  

[Date]2016-11-29
[Paper #]VLD2016-57,DC2016-51
Ultra Low Power Reconfigurable Accelerator CC-SOTB2

Koichiro Masuyama(Keio Univ.),  Naoki Ando(Keio Univ.),  Yusuke Matsushita(Keio Univ.),  Hayate Okuhara(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2016-11-29
[Paper #]VLD2016-54,DC2016-48
[Invited Talk] FPGA Development using HLS for Software Engineers

Kenichiro Mitsuda(ISP),  Hiroshi Owada(ISP),  Shinji Yamamoto(ISP),  

[Date]2016-11-29
[Paper #]RECONF2016-48
FPGA Design and Evaluation of Selector-Logic-based Butterfly Unit

Koki Ito(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2016-11-29
[Paper #]VLD2016-55,DC2016-49
SADP-Cut Aware Two-color Grid Routing

Hatsuhiko Miura(TUAT),  Mitsuru Hasegawa(TUAT),  Kunihiro Fujiyoshi(TUAT),  

[Date]2016-11-29
[Paper #]VLD2016-58,DC2016-52
EMI Performance of Power Delivery Networks in 3D TSV Integration

Yuuki Araga(AIST),  Makoto Nagata(Kobe Univ.),  Noriyuki Miura(Kobe Univ.),  Hiroaki Ikeda(Kobe Univ.),  Katsuya Kikuchi(AIST),  

[Date]2016-11-29
[Paper #]CPM2016-78,ICD2016-39,IE2016-73
[Invited Talk] Development of Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel Signal Processors by Using Direct Bonding of SOI Layers

Masahide Goto(NHK),  Yuki Honda(NHK),  Toshihisa Watabe(NHK),  Kei Hagiwara(NHK),  Masakazu Nanba(NHK),  Yoshinori Iguchi(NHK),  Takuya Saraya(Univ. Tokyo),  Masaharu Kobayashi(Univ. Tokyo),  Eiji Higurasgi(Univ. Tokyo),  Hiroshi Toshiyoshi(Univ. Tokyo),  Toshiro Hiramoto(Univ. Tokyo),  

[Date]2016-11-29
[Paper #]CPM2016-79,ICD2016-40,IE2016-74
[Invited Talk] IoT時代におけるエッジデバイスのインテリジェント化を支える脳型デバイスの重要性

Yasumitsu Orii(NAGASE & CO., LTD.),  

[Date]2016-11-29
[Paper #]
Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller

Tamakoshi Akira(Touhoku Univ.),  Masanori Natsui(Touhoku Univ.),  Takahiro Hanyu(Touhoku Univ.),  

[Date]2016-11-30
[Paper #]CPM2016-86,ICD2016-47,IE2016-81
Fully Integrated, 100-mV Minimum Input Voltage Converter with Gate-Boosted Charge Pump for Energy Harvesting

Hiroshi Fuketa(AIST),  Shin-ichi O'uchi(AIST),  Takashi Matsukawa(AIST),  

[Date]2016-11-30
[Paper #]CPM2016-87,ICD2016-48,IE2016-82
内部抵抗の大きい電源に対応するボディバイアス制御手法

Hideharu Amano(Keio Univ.),  Kouichiro Masuyama(Keio Univ.),  Hayate Okuhara(Keio Univ.),  Keita Azegami(Keio Univ.),  

[Date]2016-11-30
[Paper #]CPSY2016-55
Partitioned Hash-table and Balanced-tree based FIB Architecture

Kenta Shimazaki(Waseda Univ.),  Yuta Ukon(NTT),  Akihiko Miyazaki(NTT),  Toshitaka Tsuda(Waseda Univ.),  Hidenori Nakazato(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-65,DC2016-59
Keypoint Detection based on Learning to Rank for Robust Image Matching under Resolution Variation

Satoshi Yoshikawa(Univ. of Tsukuba),  Keisuke Kameyama(Univ. of Tsukuba),  

[Date]2016-11-30
[Paper #]CPM2016-85,ICD2016-46,IE2016-80
Fast Test Pattern Reordering Based on Weighted Fault Coverage

Shingo Inuyama(Tokyo Metropolitan Univ.),  Kazuhiko Iwasaki(Tokyo Metropolitan Univ.),  Masayuki Arai(Nihon Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-61,DC2016-55
An aging aware high-level synthesis algorithm with floorplanning

Koki Igawa(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-68,DC2016-62
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