Information and Systems-Dependable Computing(Date:2014/11/19)

Presentation
A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-Level Synthesis Algorithm for HDR Architectures

Koki IGAWA,  Shinya ABE,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-86,DC2014-40
A Method for Total Length and Length Difference Reduction for Set-pair Routing

Yuta NAKATANI,  Atsushi TAKAHASHI,  

[Date]2014/11/19
[Paper #]VLD2014-87,DC2014-41
High speed design of sub-threshold circuit by using DTMOS

Yuji FUKUDOME,  Youhua SHI,  Nozomu TOGAWA,  Kimiyoshi USAMI,  Masao YANAGISAWA,  

[Date]2014/11/19
[Paper #]VLD2014-88,DC2014-42
Don't-Care Extension in Logic Synthesis for Error Tolerant Application

Tomoya INAOKA,  Hideyuki ICHIHARA,  Tsuyoshi IWAGAKI,  Tomoo INOUE,  

[Date]2014/11/19
[Paper #]VLD2014-89,DC2014-43
Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis

Junghoon OH,  Mineo KANEKO,  

[Date]2014/11/19
[Paper #]VLD2014-90,DC2014-44
A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Net lists

Masaru OYA,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-91,DC2014-45
Magnetic Resonance (MR) Safety of Implantable Medical Device: Current Status and Future Prospect

Kagayaki KURODA,  

[Date]2014/11/19
[Paper #]VLD2014-92,CPM2014-122,ICD2014-65,CPSY2014-77,DC2014-46,RECONF2014-40
Latest Development and Future Prospect of Mobile Display Technology

Yoshiharu NAKAJIMA,  

[Date]2014/11/19
[Paper #]VLD2014-93,CPM2014-123,ICD2014-66,CPSY2014-78,DC2014-47,RECONF2014-41
Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability

Mineo KANEKO,  

[Date]2014/11/19
[Paper #]VLD2014-94,DC2014-48
Automatic Test Pattern Generation Targeting Multiple Faults under Multiple Fault Models

MASAHIRO FUJITA,  MISHCHENKO ALAN,  

[Date]2014/11/19
[Paper #]Vol.2014-SLDM-168 No.28
On Implicit Enumeration of Vector Pair Set for Synthesizing Index Generator

Yusuke MATSUNAGA,  

[Date]2014/11/19
[Paper #]VLD2014-95,DC2014-49
A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS(Invited)

Yasufumi Sakai,  Takayuki Shibasaki,  Takumi Danjo,  Hisakatsu Yamaguchi,  Toshihiko Mori,  Yoichi Koyanagi,  Hirotaka Tamura,  

[Date]2014/11/19
[Paper #]VLD2014-96,CPM2014-127,ICD2014-70,CPSY2014-84,DC2014-50,RECONF2014-45
Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open

Masayuki Arai,  Yuta Nakayama,  Kazuhiko Iwasaki,  

[Date]2014/11/19
[Paper #]VLD2014-97,DC2014-51
A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors

Atsushi HIRAI,  Toshinori HOSOKAWA,  Yukari YAMAUCHI,  Masayuki ARAI,  

[Date]2014/11/19
[Paper #]VLD2014-98,DC2014-52
A Test Point Insertion Method to Reduce Capture Power Dissipation

Yoshiyasu TAKAHASHI,  Hiroshi YAMAZAKI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2014/11/19
[Paper #]VLD2014-99,DC2014-53
A Multi Cycle Capture Test Generation Method to Reduce Capture Power Dissipation

Hiroshi YAMAZAKI,  Jun NISHIMAKI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2014/11/19
[Paper #]VLD2014-100,DC2014-54
A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning

Koki ITO,  Kazushi KAWAMURA,  Masao YANAGISAWA,  Nozomu TOGAWA,  Yutaka TAMIYA,  

[Date]2014/11/19
[Paper #]VLD2014-101,DC2014-55
Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages

Shin-ya ABE,  Youhua SHI,  Kimiyoshi USAMI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-102,DC2014-56
A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures

Yuta HAGIO,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-103,DC2014-57
A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations

Shunya HOSAKA,  Hiroshi SAITO,  

[Date]2014/11/19
[Paper #]VLD2014-104,DC2014-58
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