Information and Systems-Dependable Computing(Date:2012/11/19)

Presentation
A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation

Naohiro HAMADA,  Hiroshi SAITO,  

[Date]2012/11/19
[Paper #]VLD2012-77,DC2012-43
Controller Synthesis for Clock Improvement in Behavioral Synthesis

Ryoya SOBUE,  Yuko HARA-AZUMI,  Takuji HIEDA,  Ittetsu TANIGUCHI,  Hiroyuki TOMIYAMA,  

[Date]2012/11/19
[Paper #]VLD2012-78,DC2012-44
Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors

Zhi LI,  Hiroshi TSUTSUI,  Hiroyuki OCHI,  Takashi SATO,  

[Date]2012/11/19
[Paper #]VLD2012-79,DC2012-45
Analytical model of energy dissipation for comparing adder architectures

Nao KONISHI,  Kimiyoshi USAMI,  

[Date]2012/11/19
[Paper #]VLD2012-80,DC2012-46
Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures

Hiroyuki AKASAKA,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2012/11/19
[Paper #]VLD2012-81,DC2012-47
SAAV: Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages

Shin-ya ABE,  Youhua SHI,  Kimiyoshi USAMI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2012/11/19
[Paper #]VLD2012-82,DC2012-48
Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse

Kenji UEDA,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2012/11/19
[Paper #]VLD2012-83,DC2012-49
A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis

Tatsuya NAKASO,  Ryoko OHKUBO,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2012/11/19
[Paper #]VLD2012-84,DC2012-50
Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning

Mineo KANEKO,  

[Date]2012/11/19
[Paper #]VLD2012-85,DC2012-51
A novel efficient data structure representing shared DAG patterns

Yusuke MATSUNAGA,  

[Date]2012/11/19
[Paper #]VLD2012-86,DC2012-52
Dynamically Reconfigurable Processor (DRP) Technology : Current Status and Future Prospects

Masato MOTOMURA,  Koichiro FURUTA,  Toru AWASHIMA,  Yasunari SHIDA,  

[Date]2012/11/19
[Paper #]CPSY2012-55,DC2012-53,RECONF2012-49
On Handling Cell Placement with Adjacent Common Centroid Constraints for Analog IC Layout Design

Kunihiro FUJIYOSHI,  Keitaro UE,  

[Date]2012/11/19
[Paper #]VLD2012-88,DC2012-54
Routability-oriented Common-Centroid Capacitor Array Generation

Jing LI,  Bo YANG,  Qing DONG,  Shigetoshi NAKATAKE,  

[Date]2012/11/19
[Paper #]VLD2012-89,DC2012-55
Performance evaluation of Via Programmable Logic VPEX using P&R tool

Taku Otani,  Ryohei Hori,  Taisuke Ueoka,  Masaya Yoshikawa,  Takeshi Fujino,  

[Date]2012/11/19
[Paper #]VLD2012-90,DC2012-56
A LSI-Package-Board co-evaluation of Power noise in the Digtal LSI

Kumpei YOSHIKAWA,  Yuta SASAKI,  Kouji ICHIKAWA,  Yoshiyuki SAITO,  Makoto NAGATA,  

[Date]2012/11/19
[Paper #]VLD2012-91,DC2012-57
Rational Function Approximation Using Vector Fitting and Equivalent Circuit Synthesis of Transmission Line Characteristics

Daisuke HONDA,  Tadatoshi SEKINE,  Hideki ASAI,  

[Date]2012/11/19
[Paper #]VLD2012-92,DC2012-58
High Sensitive Detection of Low S/N ratio Signal by Bistable Potential Circuit

Hisaaki Kanai,  Wen Li,  Kengo Imagawa,  Masami Makuuchi,  Yutaka Uematsu,  Hideki Osaka,  

[Date]2012/11/19
[Paper #]VLD2012-93,DC2012-59
A 3D FPGA-Array HPC System "Vocalise" and its Performance Evaluation

Yusuke ATSUMARI,  Jiang LI,  Hiromasa KUBO,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/11/19
[Paper #]VLD2012-94,DC2012-60
Performance evaluation of a TCP/IP Hardware Stack Directly Connectable to WEB Application Circuit

Kotoko FUJITA,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/11/19
[Paper #]VLD2012-95,DC2012-61
The Fast Transient Analysis of the Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit Latency Insertion Method (LILIM)

Shingo OKADA,  Tadatoshi SEKINE,  Hideki ASAI,  

[Date]2012/11/19
[Paper #]VLD2012-96,DC2012-62
<<123>> 21-40hit(54hit)