Information and Systems-Dependable Computing(Date:2011/11/21)

Presentation
A Hardware/Software Co-Design Method Optimized for High-Level Synthesis : Application to Android Platforms

Hitoki ITO,  Kiyofumi TANAKA,  

[Date]2011/11/21
[Paper #]VLD2011-70,DC2011-46
Modeling Economics of LSI Design and Manufacturing for Selecting Test Design

Noboru SHIMIZU,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2011/11/21
[Paper #]VLD2011-71,DC2011-47
Improvement of Test Data Compression Rate for Chiba-Scan Testing by Reconstructing Scan Chain

Masato AKAGAWA,  Kazuteru NAMBA,  Hideo ITO,  

[Date]2011/11/21
[Paper #]VLD2011-72,DC2011-48
A scan chain construction method to reduce test data volume on BAST

Yun CHEN,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2011/11/21
[Paper #]VLD2011-73,DC2011-49
A BIST-Aided Scan Test Using Shifting Inverter Code and A TPG Method for Test Data Reduction

Yasuhiko OKADA,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2011/11/21
[Paper #]VLD2011-74,DC2011-50
Safe, Secure and Reliable Society by Electronics and Information Technology : What and how should we protect?(Fellow Memorial Lecture)

Shuichi SAKAI,  

[Date]2011/11/21
[Paper #]VLD2011-75,CPM2011-156,ICD2011-88,CPSY2011-42,DC2011-51,RECONF2011-48
Layout Methodology for Self-Alinged Double Patterning

Chikaaki KODAMA,  Koichi NAKAYAMA,  Toshiya KOTANI,  Shigeki NOJIMA,  Shoji MIMOTOGI,  Shinji MIYAMOTO,  

[Date]2011/11/21
[Paper #]VLD2011-76,DC2011-52
An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network-on-Chip

Hiroshi SAITO,  Tomohiro YONEDA,  Yuichi NAKAMURA,  

[Date]2011/11/21
[Paper #]VLD2011-77,DC2011-53
Ymtools : An inflastructure for research and development of logic synthesis and verification

Yusuke MATSUNAGA,  

[Date]2011/11/21
[Paper #]VLD2011-78,DC2011-54
A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning

Mineo KANEKO,  

[Date]2011/11/21
[Paper #]VLD2011-79,DC2011-55
A Hardware Development by C Source Code Visualization

Akitoshi MATSUDA,  Shinichi BABA,  Hirofumi TAKAMOTO,  

[Date]2011/11/21
[Paper #]VLD2011-80,DC2011-56
Lithography : Past, Present, and Future

Shigeki NOJIMA,  

[Date]2011/11/21
[Paper #]VLD2011-81,CPM2011-161,ICD2011-93,CPSY2011-48,DC2011-57,RECONF2011-49
Ultra Low Voltage Subthreshold Circuit Design

Masanori HASHIMOTO,  

[Date]2011/11/21
[Paper #]VLD2011-82,DC2011-58
Capture Power Reduction in Multi-cycle Test Structure

Hisato YAMAGUCHI,  Makoto MATSUZONO,  Kohei MIYASE,  Yasuo SATO,  Seiji KAJIHARA,  

[Date]2011/11/21
[Paper #]VLD2011-83,DC2011-59
On the design for testability method using Time to Digital Converter for detecting delay faults

Hiroyuki MAKIMOTO,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2011/11/21
[Paper #]VLD2011-84,DC2011-60
A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI

Satoshi KASHIWAZAKI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2011/11/21
[Paper #]VLD2011-85,DC2011-61
A Method of Thermal Uniformity Control During BIST

Eri MURATA,  Satoshi OHTAKE,  Yasuhiko NAKASHIMA,  

[Date]2011/11/21
[Paper #]VLD2011-86,DC2011-62
A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing

Yusaku YAMAMOTO,  Atsushi TAKAHASHI,  

[Date]2011/11/21
[Paper #]VLD2011-87,DC2011-63
An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations

Yiqiang SHENG,  Atsushi TAKAHASHI,  Shuichi UENO,  

[Date]2011/11/21
[Paper #]VLD2011-88,DC2011-64
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

Takao KAWANO,  Naoya ONIZAWA,  Atsushi Matsumoto,  Takahiro HANYU,  

[Date]2011/11/21
[Paper #]VLD2011-89,DC2011-65
<<123>> 21-40hit(45hit)