Information and Systems-Dependable Computing(Date:2010/11/22)

Presentation
ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding

Mineo KANEKO,  

[Date]2010/11/22
[Paper #]VLD2010-75,DC2010-42
A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description

Ryoichi INOUE,  Hiroaki FUJIWARA,  Toshinori HOSOKAWA,  Hideo FUJIWARA,  

[Date]2010/11/22
[Paper #]VLD2010-76,DC2010-43
Adjacent Insertion and Its Effectiveness in Code-Based 3-D Placement

Shin UESUGI,  Mineo KANEKO,  

[Date]2010/11/22
[Paper #]VLD2010-77,DC2010-44
On pruning rules in exact algorithms for the minimum rectilinear Steiner arborescence problem

Masayuki NAGASE,  Toshihiko TAKAHASHI,  

[Date]2010/11/22
[Paper #]VLD2010-78,DC2010-45
Analysis of Channel Decomposition for Structured Analog Layout and Low-power Applications

Bo YANG,  Qing DONG,  Jing LI,  Shigetoshi NAKATAKE,  

[Date]2010/11/22
[Paper #]VLD2010-79,DC2010-46
Develop A Clock Tree Generator into Open-source CAD System

Takuya HIGUCHI,  Jun'ichiro OGANE,  Naohiko SHIMIZU,  

[Date]2010/11/22
[Paper #]VLD2010-80,DC2010-47
Optimal Adder Architecture in Ultra Low Voltage Domain

Nao KONISHI,  Masaru KUDO,  Kimiyoshi USAMI,  

[Date]2010/11/22
[Paper #]VLD2010-81,DC2010-48
A proposal for A VLSI model for evaluation of rush current by power gating

Hiroto Yamauchi,  Jyunki Miyajima,  Tomohiko Sumi,  Masahiro Fukui,  Shuji Tsukiyama,  

[Date]2010/11/22
[Paper #]VLD2010-82,DC2010-49
Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control

Xin MAN,  Takashi HORIYAMA,  Tomoo KIMURA,  Koji KAI,  Shinji KIMURA,  

[Date]2010/11/22
[Paper #]VLD2010-83,DC2010-50
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