Information and Systems-Dependable Computing(Date:2002/11/21)

Presentation
The Width Constrained Placement by the Simulated Annealing with the Sequence-Pair Encoding

Satoshi TAYU,  Mineo KANEKO,  

[Date]2002/11/21
[Paper #]DC2002-52
The method of checking connections between FPGAs/PLDs

Koichi TANDA,  Akitsugu NAKAYAMA,  

[Date]2002/11/21
[Paper #]DC2002-53
An Architecture for Digital Sample Interpolator Application to Bluetooth CVSD Audio Signal Interface

Takeo YASUDA,  

[Date]2002/11/21
[Paper #]DC2002-54
Implementation of Protocol Booster with Dynamically Reconfigurable System

Kazunori SHIMIZU,  XIAOMEI Chen,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2002/11/21
[Paper #]DC2002-55
A Study on the Circuit Implementation of an Asynchronous LSI with a Self-Reconfiguration Feature

Ryusuke KONISHI,  Hideyuki ITO,  Hiroshi NAKADA,  Akira NAGOYA,  

[Date]2002/11/21
[Paper #]DC2002-56
A Processor System for Embedded Control System on FPGA

Hideo ARAKI,  Toshiro KUTSUWA,  Katsumi HARASHIMA,  

[Date]2002/11/21
[Paper #]DC2002-57
Development of Cable Modem based on DOCSIS1.1 : Investigation of architecture for error detection code generation in MAC Upstream Operation

Tatsuji Ishii,  Machiya Kumazawa,  Toshihiko Fukuoka,  Hiroyuki Senda,  Takehiro Kamada,  

[Date]2002/11/21
[Paper #]DC2002-58
New Dynamic Circuits masked Precharge Phase for High Throughput Datapath : Guide to the Technical Report and Template

Masayuki TSUKISAKA,  Masashi IMAI,  Takashi NANYA,  

[Date]2002/11/21
[Paper #]DC2002-59
High-Speed Modular Arithmetic Accelerator for RSA Public Key Cryptosystem

Yuhki KAJIWARA,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2002/11/21
[Paper #]DC2002-60
A Modulo M Multiplier/Divider

Marcelo E. KAIHARA,  Naofumi TAKAGI,  

[Date]2002/11/21
[Paper #]DC2002-61
Multi-Port-Cache Design with Hierarchical Multi-Bank Memory

Koh JOHGUCHI,  Zhaomin ZHU,  Hans Jurgen MATTAUSCH,  Tetsushi KOIDE,  Tai HIRAKAWA,  Tetsuo HIRONAKA,  

[Date]2002/11/21
[Paper #]DC2002-62
Small-Area Multi-Port Register Files with Multi-Bank Structure

Hiroshi UCHIDA,  Yosuke MITANI,  Hans Jurgen MATTAUSCH,  Tetsushi KOIDE,  Tetsuo HIRONAKA,  

[Date]2002/11/21
[Paper #]DC2002-63
A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search

Yuji YANO,  Masahiro MIZOKAMI,  Minoru HONDA,  Tetsushi KOIDE,  Hans Jurgen MATTAUSCH,  

[Date]2002/11/21
[Paper #]DC2002-64
A Behavioral Synthesis System for Extended CAM Processors

Takao TOTSUKA,  Yuichiro ISHIKAWA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2002/11/21
[Paper #]DC2002-65
Soft-core Processor with MIPS R3000 Compatible Instruction Set and its Applications

Tetsuo HIRONAKA,  Takahiro SASAKI,  Naoki NISHIMURA,  

[Date]2002/11/21
[Paper #]DC2002-66
Development of Multiplier and Divider IPs

Tomohide MIZUNO,  Masayuki SHINOHARA,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2002/11/21
[Paper #]DC2002-67
Development of IP Library of IEEE754 Std Single-Precision Floating-Point Dividers

Hiroyuki OCHI,  Tatsuya SUZUKI,  Sayaka MATSUNAGA,  Yoichi KAWANO,  Takao TSUDA,  

[Date]2002/11/21
[Paper #]DC2002-68
A wiring delay torelant input module IP which manages miss-alignment of data lane

Konosuke WATANABE,  Jun-ichiro TSUCHIYA,  Hideharu AMANO,  

[Date]2002/11/21
[Paper #]DC2002-69
Consideration about IP Supply of Hardware Systems Utilizing Spec-Design CAD

Kentaro YOSHIKAWA,  Yoshikazu MIYANAGA,  Shingo YOSHIZAWA,  

[Date]2002/11/21
[Paper #]DC2002-70
Flexible Hardware Model : A Hardware Model for IP reuse and its Database Management System FHM-DBMS

Yoshinori TAKEUCHI,  Kyoto UEDA,  Yukinori YAMANE,  Akichika Shiomi,  Masaharu IMAI,  

[Date]2002/11/21
[Paper #]DC2002-71
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