Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2008/11/10)

Presentation
Improving the Accuracy of Rule-based Equivalence Checking of High-level Descriptions by Identifying Potential Internal Equivalences

Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2008/11/10
[Paper #]VLD2008-78,DC2008-46
Generation of High Coverage Property Set Using Counterexamples

Takeshi MATSUMOTO,  Yeonbok LEE,  Hiroaki YOSHIDA,  Hisashi YOMIYA,  Masahiro FUJITA,  

[Date]2008/11/10
[Paper #]VLD2008-79,DC2008-47
A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment

Kazuko HIRAMOTO,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2008/11/10
[Paper #]VLD2008-80,DC2008-48
A Hybrid Delay Scan for Delay Testing Based on Propagation Dominance

Tomomi NUWA,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2008/11/10
[Paper #]VLD2008-81,DC2008-49
A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains

Takashi YOSHIDA,  Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2008/11/10
[Paper #]VLD2008-82,DC2008-50
Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations

Yuki TODA,  Nagisa ISHIURA,  Kousuke SONE,  

[Date]2008/11/10
[Paper #]VLD2008-83,DC2008-51
A Multiplexer Reducing Algorithm in Floorplan-Aware High-level Synthesis for Distributed-Register Architectures

Tetsuya ENDO,  Akira OHCHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2008/11/10
[Paper #]VLD2008-84,DC2008-52
Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints

Keisuke INOUE,  Mineo KANEKO,  Tsuyoshi IWAGAKI,  

[Date]2008/11/10
[Paper #]VLD2008-85,DC2008-53
Enlarging The Solution Space For Schedulability Based On Skew Optimization

Takayuki OBATA,  Mineo KANEKO,  

[Date]2008/11/10
[Paper #]VLD2008-86,DC2008-54
Accuracy and Speed Improvement of Random Walk Simulation Using Walk Sharing and Return-to-Start Transient Analysis Technique

Hitoshi MIWA,  Goro SUZUKI,  

[Date]2008/11/10
[Paper #]VLD2008-87,DC2008-55
Delay analysis method using stochastic process

Kazuki HORI,  Goro SUZUKI,  

[Date]2008/11/10
[Paper #]VLD2008-88,DC2008-56
Power Noise Analysis Acceleration Technique by Linear Programming Method

Takeshi GOMAKUBO,  Goro SUZUKI,  

[Date]2008/11/10
[Paper #]VLD2008-89,DC2008-57
Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors

Koei TAKADA,  Masashi IMAI,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2008/11/10
[Paper #]VLD2008-90,DC2008-58
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