IEICE Technical Committee

Engineering Sciences/NOLTA-Hardware Security(Date:2023/03/01)

Presentation

Reducing Conflict Misses with Multiple Indexings in Compressed Caches

Tasuku Fukami(UTokyo), Shinya Takamaeda(UTokyo),

[Date]2023-03-02
[Paper #]VLD2022-98,HWS2022-69

Hiding Memory Structures for IP Protection

Sun Tanaka(UTokyo), Shinya Takamaeda(UTokyo),

[Date]2023-03-02
[Paper #]VLD2022-96,HWS2022-67

[Memorial Lecture] DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits [Memorial lecture]

Dehua Liang(Osaka Univ.), Hiromitsu Awano(Kyoto Univ.), Noriyuki Miura(Osaka Univ.), Jun Shiomi(Osaka Univ.),

[Date]2023-03-02
[Paper #]VLD2022-93,HWS2022-64

近似演算器を用いたCGRAとアプリケーションマッピングの協調設計

Kaito Kutsuna(Univ. Tokyo), Takuya Kojima(Univ. Tokyo), Hideki Takase(Univ. Tokyo), Hiroshi Nakamura(Univ. Tokyo),

[Date]2023-03-02
[Paper #]VLD2022-88,HWS2022-59

Multiple Constant Convolution with Minimum Number of Full Adders.

Kota Kuga(UTokyo), Shinya Takamaeda(UTokyo),

[Date]2023-03-02
[Paper #]VLD2022-97,HWS2022-68

Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution

Mineo Kaneko(JAIST),

[Date]2023-03-02
[Paper #]VLD2022-89,HWS2022-60

Implementation of power-outage tolerant VLSI system using asynchronous circuits

Masashi Imai(Hirosaki Univ.),

[Date]2023-03-02
[Paper #]VLD2022-86,HWS2022-57

Ryusei Eda(Waseda Univ.), Kota Hisafuru(Waseda Univ.), Ryotaro Negishi(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2023-03-03
[Paper #]VLD2022-112,HWS2022-83

Hibiki Nakanishi(Waseda Univ.), Kota Hisafuru(Waseda Univ.), Ryotaro Negishi(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2023-03-03
[Paper #]VLD2022-113,HWS2022-84

Approximate Computingにおける回路の高速化のためのネット対のマージ手法

Yusei Yano(Univ. of Aizu), Shinji Nozaki(Univ. of Aizu), Tomohide Aizawa(Univ. of Aizu), Yukihide Kohira(Univ. of Aizu),

[Date]2023-03-03
[Paper #]VLD2022-103,HWS2022-74

A Seed Selection Method for Minimizing Test Execution Time in Logic BIST Using Pseudo-Boolean Optimization

Rei Miura(Nihon Univ.), Toshinori Hosokawa(Nihon Univ.), Masayoshi Yoshimura(Kyoto Sangyou Univ.),

[Date]2023-03-03
[Paper #]VLD2022-105,HWS2022-76

Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits

Jiaxuan Lu(Nagoya Univ.), Yutaka Masuda(Nagoya Univ.), Tohru Ishihara(Nagoya Univ.),

[Date]2023-03-03
[Paper #]VLD2022-104,HWS2022-75

N/A

Yuka Ikegami(Waseda Univ.), Kazuki Yamashita(Waseda Univ.), Kento Hasegawa(KDDI Research, Inc.), Kazuhide Fukushima(KDDI Research, Inc.), Shinsaku Kiyomoto(KDDI Research, Inc.), Nozomu Togawa(Waseda Univ.),

[Date]2023-03-03
[Paper #]VLD2022-108,HWS2022-79

Toggle-based simulation of side-channel attack against multiplier for pairing-based cryptography

Saito Kikuoka(Tokyo Univ.), Makoto Ikeda(Tokyo Univ.),

[Date]2023-03-03
[Paper #]VLD2022-109,HWS2022-80

Takuma Yabe(Waseda Univ.), Kota Hisafuru(Waseda Univ.), Ryotaro Negishi(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2023-03-03
[Paper #]VLD2022-114,HWS2022-85

High-Performance and Programmer-Friendly Secure Non-Volatile Memory using Temporal Memory-Access Redirection

Ryo Koike(UTokyo), Shinya Takamaeda(UTokyo),

[Date]2023-03-03
[Paper #]VLD2022-106,HWS2022-77

Design optimization of TFHE-based 4+ input homomorphic logic gates by error controlling

Yinfan Zhao(Tokyo Univ.), Makoto Ikeda(Tokyo Univ.),

[Date]2023-03-03
[Paper #]VLD2022-110,HWS2022-81

Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints

Zuan Jo(Tokyo Tech), Satoshi Tayu(Tokyo Tech), Atsushi Takahashi(Tokyo Tech), Molongo Mathieu(JEDAT), Makoto Minami(JEDAT), Katsuya Nishioka(JEDAT),

[Date]2023-03-03
[Paper #]VLD2022-102,HWS2022-73

A Logic Locking Method based on Function Modification Circuit

Yohei Noguchi(Kyoto Sangyo Univ.), Masayoshi Yoshimura(Kyoto Sangyo Univ.), Rei Miura(Nihon Univ.), Toshinori Hosokawa(Nihon Univ.),

[Date]2023-03-03
[Paper #]VLD2022-107,HWS2022-78

Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA

Mika Sakai(Ritsumeikan Univ.), Tatsuya Oyama(Ritsumeikan Univ.), Kota Yoshida(Ritsumeikan Univ.), Yohei Hori(AIST), Toshihiro Katashita(AIST), Masayoshi Shirahata(Ritsumeikan Univ.), Takeshi Fujino(Ritsumeikan Univ.),

[Date]2023-03-03
[Paper #]VLD2022-111,HWS2022-82