Electronics-Integrated Circuits and Devices(Date:2018/12/05)

Presentation
Millimeter wave band CMOS low noise amplifier design

Kyoya Takegawa(Hiroshima Univ.),  Shuhei Amakawa(Hiroshima Univ.),  Takeshi Yoshida(Hiroshima Univ.),  Minoru Fujishima(Hiroshima Univ.),  

[Date]2018-12-06
[Paper #]CPM2018-89,ICD2018-50,IE2018-68
An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server

Shoko Ohteru(NTT),  Saki Hatta(NTT),  Tomoaki Kawamura(NTT),  Koji Yamazaki(NTT-AT),  Takahiro Hatano(NTT),  Akihiko Miyazaki(NTT),  Koyo Nitta(NTT),  

[Date]2018-12-06
[Paper #]VLD2018-55,DC2018-41
Multi-FPGA implementation of deep learning applications

Kazusa Musha(Keio Univ.),  Akram Ben Ahmed(Keio Univ.),  Kudoh Tomohiro(Univ. of Tokyo),  Hideharu Amano(Keio Univ.),  

[Date]2018-12-06
[Paper #]RECONF2018-40
On the Generation of Random Capture Safe Test Vectors Using Neural Networks

Sayuri Ochi(Nihon Univ.),  Kenichirou Misawa(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Yukari Yamauchi(Nihon Univ.),  Masayuki Arai(Nihon Univ.),  

[Date]2018-12-06
[Paper #]VLD2018-51,DC2018-37
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips

Takaaki Kato(KIT),  Senling Wang(Ehime Univ.),  Yasuo Sato(KIT),  Seiji Kajihara(KIT),  

[Date]2018-12-06
[Paper #]VLD2018-57,DC2018-43
Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis

Sho Yuasa(Hiroshima City Univ.),  Tsuyoshi Iwagaki(Hiroshima City Univ.),  Hideyuki Ichihara(Hiroshima City Univ.),  Tomoo Inoue(Hiroshima City Univ.),  

[Date]2018-12-06
[Paper #]VLD2018-59,DC2018-45
2^nRRR:高度な並び替えにより誤り耐性を強化したストカスティック数複製器

Ryota Ishikawa(Waseda Univ.),  Masashi Tawada(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2018-12-06
[Paper #]VLD2018-52,DC2018-38
Stochastic Number Generation Considering Trade-off between Error and Overhead

Yudai Sakamoto(Ritsumeikan Univ.),  Shigeru Yamashita(Ritsumeikan Univ.),  

[Date]2018-12-06
[Paper #]VLD2018-47,DC2018-33
Transparent Acceleration Method for Network Function Virtualization Using FPGA

Yoshikazu Watanabe(NEC),  Yuki Kobayashi(NEC),  Takashi Takenaka(NEC),  Baba Hiroshi(NEC),  

[Date]2018-12-06
[Paper #]RECONF2018-38
Design guideline of ground structure in slow wave transmission line

Tomohiro Kobayashi(Hiroshima Univ),  Syuhei Amakawa(Hiroshima Univ),  Takeshi Yoshida(Hiroshima Univ),  Minoru Fujishima(Hiroshima Univ),  

[Date]2018-12-06
[Paper #]CPM2018-88,ICD2018-49,IE2018-67
A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique

Akira Jinguji(titech),  Simpei Sato(titech),  Hiroki Nakahara(titech),  

[Date]2018-12-06
[Paper #]RECONF2018-41
Resources Utilization of Fine-grained Overlay Architecture

Theingi Myint(Kumamoto),  Qian Zhao(Kyutech),  Motoki Amagasaki(Kumamoto),  Masahiro Iida(Kumamoto),  Toshinori Sueyoshi(Kumamoto),  

[Date]2018-12-06
[Paper #]RECONF2018-37
Triple modular redundancy optically reconfigurable gate array

Toru Yoshinaga(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2018-12-06
[Paper #]RECONF2018-43
FPGA implementation of a robot control algorithm

Yusuke Takaki(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  Kentaro Sano(Riken),  

[Date]2018-12-06
[Paper #]RECONF2018-44
Hardware implementation of ECG signals outlier detector trained by Sparse Robust Deep Autoencoder

Naoto Soga(Titech),  Shimpei Sato(Titech),  Hiroki Nakahara(Titech),  

[Date]2018-12-06
[Paper #]RECONF2018-42
An efficient SAT-attack algorithm against logic encryption

Yusuke Matsunaga(Kyushu Univ.),  Masayoshi Yoshimura(Kyoto Sangyo Univ.),  

[Date]2018-12-06
[Paper #]VLD2018-60,DC2018-46
An Evaluation of Acceleration Framework to Exploit TCAM implemented on FPGA

Takefumi Miyoshi(WasaLab/e-trees.Japan),  Satoshi Funada(e-trees.Japan),  

[Date]2018-12-06
[Paper #]RECONF2018-39
変分混合ガウスモデルアクセラレータ設計のための変分推論アルゴリズムの解析

Hiroki Nishimoto(NAIST),  Takashi Nakada(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2018-12-06
[Paper #]VLD2018-62,DC2018-48
A Hybrid Method Using Monte-Carlo Tree Search and Gibbs Sampling Method for Solving Motif Extraction Problems

Yusuke Yuasa(HCU),  Shinobu Nagayama(HCU),  Masato Inagi(HCU),  Shin'ichi Wakabayashi(HCU),  

[Date]2018-12-06
[Paper #]VLD2018-61,DC2018-47
[Invited Talk] What I should do beside dedicated AI hardwares

Yasuhiko Nakashima(NAIST),  

[Date]2018-12-06
[Paper #]CPSY2018-37
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