IEICE Technical Committee

Electronics-Integrated Circuits and Devices(Date:2007/08/16)

Presentation

Influence of metal gate : high-k technology introduction on MOSFET device characteristics beyond 32nm node

Masato KOYAMA, Masahiro KOIKE, Yuuichi KAMIMUTA, Masamichi SUZUKI, Kosuke Tatsumura, Yoshinori TSUCHIYA, Reika ICHIHARA, Masakazu GOTO, Koji NAGATOMO, Atsushi AZUMA, Shigeru KAWANAKA, Kazuaki NAKAJIMA, Katsuyuki SEKINE,

[Date]2007/8/16
[Paper #]SDM2007-159,ICD2007-87

Experimental Study on Mobility Universality in (100) Ultra Thin Body nMOSFET with SOI thickness of 5nm

Ken SHIMIZU, Toshiro HIRAMOTO,

[Date]2007/8/16
[Paper #]SDM2007-160,ICD2007-88

A Test Structure for Analysis of Asymmetry and Orientation Dependence of MOSFETs

Toshihiro MATSUDA, Yuya SUGIYAMA, Hideyuki IWATA, Takashi OHZONE,

[Date]2007/8/16
[Paper #]SDM2007-161,ICD2007-89

Towards Great Nanoelectronics Country, Japan

Hisatsune WATANABE,

[Date]2007/8/16
[Paper #]SDM2007-161,ICD2007-90

Design of High Density LSI with Three-Dimensional Transistor FinFET : Effect of Pattern Area Reduction with CMOS Cell Library

Keisuke Okamoto, Keisuke Koizumi, Yuu Hirosima, Shigeyoshi Watanabe,

[Date]2007/8/16
[Paper #]SDM2007-163,ICD2007-91

Design Method of High Density System LSI with Three-Dimensional FinFET type DTMOS : Reduction of Pattern Area

Yu HIROSHIMA, Shigeyoshi WATANABE, Keisuke OKAMOTO, Keisuke KOIZUMI,

[Date]2007/8/16
[Paper #]SDM2007-164,ICD2007-92

0.7V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32nm Node

H. Onoda, K. Miyashita, T. Nakayama, T. Kinoshita, H. Nishimura, A. Azuma, S. Yamada, F. Matsuoka,

[Date]2007/8/16
[Paper #]SDM2007-165,ICD2007-93

SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for suppressing read disturbance and write-current dispersion

Katsuya Miura, Takayuki Kawahara, Riichiro Takemura, Jun Hayakawa, Michihiko Yamanouchi, Shoji Ikeda, Ryutaro Sasaki, Kenchi Ito, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno,

[Date]2007/8/16
[Paper #]SDM2007-166,ICD2007-94

An Area-Conscious Low-Voltage-Oriented 8T SRAM Design under DVS Environment

Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Yusuke IGUCHI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO,

[Date]2007/8/16
[Paper #]SDM2007-167,ICD2007-95

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu,

[Date]2007/8/16
[Paper #]SDM2007-168,ICD2007-96

A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology

Koh JOHGUCHI, Yuya MUKUDA, Shinya IZUMI, Hans Jurgen MATTAUSCH, Testushi KOIDE,

[Date]2007/8/16
[Paper #]SDM2007-169,ICD2007-97

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