Electronics-Integrated Circuits and Devices(Date:2004/11/25)

Presentation
Asynchronous Circuit Synthesis from Specification Language Balsa

Atsushi MATSUMOTO,  Manabu KATO,  Hiroomi ONDA,  Tomohiro YONEDA,  

[Date]2004/11/25
[Paper #]VLD2004-79,ICD2004-165,DC2004-65
Asynchronous Data-Path Circuit Synthesis by Using Force-Directed Scheduling Algorithm and Consideration to Improve Efficiency

Hiroshi SAITO,  Tomohiro YONEDA,  

[Date]2004/11/25
[Paper #]VLD2004-80,ICD2004-166,DC2004-66
A Synthesis Method of Control Circuits for Pipelined Asynchronous Prosessors

Yozo ONISHI,  Hiroto KAGOTANI,  Yuji SUGIYAMA,  Takuji OKAMOTO,  

[Date]2004/11/25
[Paper #]VLD2004-81,ICD2004-167,DC2004-67
A High-level Synthesis Algorithm with Floorplaning for a Distributed-register Architecture

Akira TANAKA,  Jumpei UCHIDA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2004/11/25
[Paper #]VLD2004-82,ICD2004-168,DC2004-68
Practical Techniques for Automatic Detection of Timing Exception Paths in Sequential Circuits

Hiroyuki HIGUCHI,  Yusuke MATSUNAGA,  

[Date]2004/11/25
[Paper #]VLD2004-83,ICD2004-169,DC2004-69
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications

Munehiro MATSUURA,  Tsutomu SASAO,  

[Date]2004/11/25
[Paper #]VLD2004-84,ICD2004-170,DC2004-70
A Design Algorithm for Sequential Circuit Synthesis using LUT Ring

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2004/11/25
[Paper #]VLD2004-85,ICD2004-171,DC2004-71
An Encoding Method for Rail Outputs in LUT cascades

Shinya NAGAYASU,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2004/11/25
[Paper #]VLD2004-86,ICD2004-172,DC2004-72
Transformation-Based Logic Design for RSFQ Logic Circuits

Shigeru YAMASHITA,  Katsunori TANAKA,  Hideyuki TAKADA,  

[Date]2004/11/25
[Paper #]VLD2004-87,ICD2004-173,DC2004-73
An Optimum Implementation of FFT Multiplier

Syunji YAZAKI,  Koki ABE,  

[Date]2004/11/25
[Paper #]VLD2004-88,ICD2004-174,DC2004-74
Development of a Multiplier Module Generator Using Arithmetic Description Language

Kazuya ISHIDA,  Naofumi HOMMA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]2004/11/25
[Paper #]VLD2004-89,ICD2004-175,DC2004-75
Synthesis of Digit-Recurrence Algorithms for Arithmetic Circuits

Fumio KUMAZAWA,  Naofumi TAKAGI,  

[Date]2004/11/25
[Paper #]VLD2004-90,ICD2004-176,DC2004-76
Design of Fast Montgomery Modular Multipliers using Parallel Addition

Kentaro TAIRA,  Hiroyuki SHIMAJIRI,  Takeo YOSHIDA,  

[Date]2004/11/25
[Paper #]VLD2004-91,ICD2004-177,DC2004-77
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer

Satoshi KOMATSU,  Masahiro FUJITA,  

[Date]2004/11/25
[Paper #]VLD2004-92,ICD2004-178,DC2004-78
A Case Study of Power Estimation of MP3 Decoder

Yutaka TAMIYA,  Yoshinori TOMITA,  Tasuya YAMAMOTO,  

[Date]2004/11/25
[Paper #]VLD2004-93,ICD2.004-179,DC2004-79
A Leakage Current Reduction Technique by Optimizing Waiting Time Dynamically in Self-Timed Cut-Off Scheme

Akihiko HIGUCHI,  Kazutoshi KOBAYASHI,  Hidetoshi ONODERA,  

[Date]2004/11/25
[Paper #]VLD2004-94,ICD2004-180,DC2004-80
A Power Reduction Technique for FFT in OFDM Based Wireless Communication Systems

Kosuke TARUMI,  Lai KWOK PENG,  Masayuki TOKUNAGA,  Hiroto YASUURA,  

[Date]2004/11/25
[Paper #]VLD2004-95,ICD2004-181,DC2004-81
An Energy Reduction Technique for Digital Wireless Communication Systems

Kosuke TARUMI,  Yusuke MAJIMA,  Masanori MUROYAMA,  Hiroto YASUURA,  

[Date]2004/11/25
[Paper #]VLD2004-96,ICD2004-182,DC2004-82
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