IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

Technical Committee on VLSI Design Technologies (VLD)  (2008)

Chair: Daisuke Fukuda (Fujitsu Labs.) Vice Chair: Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary: Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant: Takuma Nishimoto (Hitachi)

Search Results: Keywords 'from:2009-03-11 to:2009-03-11'

[Go to Official VLD Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 43  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2009-03-11
10:30
Okinawa   Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution
Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126
This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] VLD2008-126
pp.1-6
VLD 2009-03-11
10:55
Okinawa   Random Testing for Arithmetic Optimization of C compilers
Hironobu Awazu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2008-127
This article presents random testing of C compilers focusing on arithmetic optimization. It tests if code generation and... [more] VLD2008-127
pp.7-10
VLD 2009-03-11
11:20
Okinawa   Execution Trace Mining for Intratask DVFS in Embedded Systems
Tomohiro Tatematsu, Tetsuo Yokoyama, Takehiko Kikuchi, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) VLD2008-128
We propose execution trace mining for intratask DVFS (dynamic voltage and frequency scaling) in embedded systems to effe... [more] VLD2008-128
pp.11-16
VLD 2009-03-11
13:00
Okinawa   [Invited Talk] Model-Based Development for automotive control systems -- Modeling Technique of microcontroller --
Yasuo Sugure, Shigeru Oho (Hitachi Ltd.) VLD2008-129
 [more] VLD2008-129
pp.17-22
VLD 2009-03-11
14:00
Okinawa   Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2008-130
With the advance of process technology, delay variations have become a serious problem. Recently, the register assignmen... [more] VLD2008-130
pp.23-28
VLD 2009-03-11
14:25
Okinawa   Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints
Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) VLD2008-131
In this paper, a pipeline scheduling algorithm for minimizing total circuit area under throughput constraint
is present... [more]
VLD2008-131
pp.29-34
VLD 2009-03-11
14:50
Okinawa   Fault Tolerant Datapath Synthesis Starting with Triple Algorithm Redundancy
Yutaka Tsuboishi, Mineo Kaneko (JAIST) VLD2008-132
In this paper, we investigate the problem to synthesize a fault-tolerant datapath from a triplicated computation algorit... [more] VLD2008-132
pp.35-40
VLD 2009-03-11
15:15
Okinawa   On the Minimization of Input Variables for Incompletely Specified Index Generation Functions
Takaaki Nakamura, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.) VLD2008-133
This paper shows a method to reduce the numbers of input variables to represent incompletely specified index generation ... [more] VLD2008-133
pp.41-46
VLD 2009-03-11
15:50
Okinawa   A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool
Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-134
Clock trees for general synchronous framework can be synthesized by using a clock tree synthesis (CTS) engine in EDA sys... [more] VLD2008-134
pp.47-52
VLD 2009-03-11
16:15
Okinawa   A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits
Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] VLD2008-135
pp.53-58
VLD 2009-03-11
16:40
Okinawa   A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-136
Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity in... [more] VLD2008-136
pp.59-64
VLD 2009-03-11
17:05
Okinawa   Fast Optimization on Minimum Perturbation Placement Realization
Yuki Kouno, Yasuhiro Takashima (The Univ. of Kitakyushu), Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-137
 [more] VLD2008-137
pp.65-70
VLD 2009-03-11
17:30
Okinawa   Delay Estimation of Sub-path under Path-delay Test
Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.) VLD2008-138
 [more] VLD2008-138
pp.71-75
VLD 2009-03-12
09:15
Okinawa   Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX
Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2008-139
We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] VLD2008-139
pp.77-82
VLD 2009-03-12
09:40
Okinawa   The implementation of DES cryptographic circuit and the evaluation of DPA attack resistance using Domino-RSL technique
Kenji Kojima, Kazuki Okuyama, Yuki Makino, Takeshi Fujino (Ritsumeikandai Univ.) VLD2008-140
To achieve cryptographic circuit that has tamper resistance, it is necessary that we take a LSI design considered counte... [more] VLD2008-140
pp.83-88
VLD 2009-03-12
10:05
Okinawa   Differential Power Analysis of bit-value against cipher implementation on FPGA
Kazuki Okuyama, Kenji Kojima, Yuki Makino, Takeshi Fujino (Ritsumei Univ.) VLD2008-141
DPA side-channel attack is the encryption-key estimation method by the statistical analysis on circuit consumption power... [more] VLD2008-141
pp.89-94
VLD 2009-03-12
10:30
Okinawa   A Formal Verification Method for On-Chip Programmable Interconnect
Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2008-142
As the development cost increases, programmable devices such as FPGAs are becoming critically important. A key componen... [more] VLD2008-142
pp.95-100
VLD 2009-03-12
11:05
Okinawa   High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit
Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT) VLD2008-143
(To be available after the conference date) [more] VLD2008-143
pp.101-106
VLD 2009-03-12
11:30
Okinawa   A memory-reduction method for multi-rate LDPC encoder
Wenming Tang, Xianghui WEI, Satoshi Goto (Waseda Univ.) VLD2008-144
 [more] VLD2008-144
pp.107-110
VLD 2009-03-12
13:00
Okinawa   Emulation of Sequential Circuits by a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs)
and a programmable in... [more]
VLD2008-145
pp.111-116
 Results 1 - 20 of 43  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan