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Technical Committee on VLSI Design Technologies (VLD)  (2008)

Chair: Daisuke Fukuda (Fujitsu Labs.) Vice Chair: Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary: Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant: Takuma Nishimoto (Hitachi)

Search Results: Keywords 'from:2009-03-11 to:2009-03-11'

[Go to Official VLD Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 43  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2009-03-11
Okinawa   Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution
Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126
This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] VLD2008-126
VLD 2009-03-11
Okinawa   Random Testing for Arithmetic Optimization of C compilers
Hironobu Awazu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2008-127
This article presents random testing of C compilers focusing on arithmetic optimization. It tests if code generation and... [more] VLD2008-127
VLD 2009-03-11
Okinawa   Execution Trace Mining for Intratask DVFS in Embedded Systems
Tomohiro Tatematsu, Tetsuo Yokoyama, Takehiko Kikuchi, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) VLD2008-128
We propose execution trace mining for intratask DVFS (dynamic voltage and frequency scaling) in embedded systems to effe... [more] VLD2008-128
VLD 2009-03-11
Okinawa   [Invited Talk] Model-Based Development for automotive control systems -- Modeling Technique of microcontroller --
Yasuo Sugure, Shigeru Oho (Hitachi Ltd.) VLD2008-129
 [more] VLD2008-129
VLD 2009-03-11
Okinawa   Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2008-130
With the advance of process technology, delay variations have become a serious problem. Recently, the register assignmen... [more] VLD2008-130
VLD 2009-03-11
Okinawa   Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints
Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) VLD2008-131
In this paper, a pipeline scheduling algorithm for minimizing total circuit area under throughput constraint
is present... [more]
VLD 2009-03-11
Okinawa   Fault Tolerant Datapath Synthesis Starting with Triple Algorithm Redundancy
Yutaka Tsuboishi, Mineo Kaneko (JAIST) VLD2008-132
In this paper, we investigate the problem to synthesize a fault-tolerant datapath from a triplicated computation algorit... [more] VLD2008-132
VLD 2009-03-11
Okinawa   On the Minimization of Input Variables for Incompletely Specified Index Generation Functions
Takaaki Nakamura, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.) VLD2008-133
This paper shows a method to reduce the numbers of input variables to represent incompletely specified index generation ... [more] VLD2008-133
VLD 2009-03-11
Okinawa   A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool
Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-134
Clock trees for general synchronous framework can be synthesized by using a clock tree synthesis (CTS) engine in EDA sys... [more] VLD2008-134
VLD 2009-03-11
Okinawa   A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits
Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] VLD2008-135
VLD 2009-03-11
Okinawa   A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-136
Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity in... [more] VLD2008-136
VLD 2009-03-11
Okinawa   Fast Optimization on Minimum Perturbation Placement Realization
Yuki Kouno, Yasuhiro Takashima (The Univ. of Kitakyushu), Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-137
 [more] VLD2008-137
VLD 2009-03-11
Okinawa   Delay Estimation of Sub-path under Path-delay Test
Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.) VLD2008-138
 [more] VLD2008-138
VLD 2009-03-12
Okinawa   Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX
Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2008-139
We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] VLD2008-139
VLD 2009-03-12
Okinawa   The implementation of DES cryptographic circuit and the evaluation of DPA attack resistance using Domino-RSL technique
Kenji Kojima, Kazuki Okuyama, Yuki Makino, Takeshi Fujino (Ritsumeikandai Univ.) VLD2008-140
To achieve cryptographic circuit that has tamper resistance, it is necessary that we take a LSI design considered counte... [more] VLD2008-140
VLD 2009-03-12
Okinawa   Differential Power Analysis of bit-value against cipher implementation on FPGA
Kazuki Okuyama, Kenji Kojima, Yuki Makino, Takeshi Fujino (Ritsumei Univ.) VLD2008-141
DPA side-channel attack is the encryption-key estimation method by the statistical analysis on circuit consumption power... [more] VLD2008-141
VLD 2009-03-12
Okinawa   A Formal Verification Method for On-Chip Programmable Interconnect
Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2008-142
As the development cost increases, programmable devices such as FPGAs are becoming critically important. A key componen... [more] VLD2008-142
VLD 2009-03-12
Okinawa   High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit
Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT) VLD2008-143
(To be available after the conference date) [more] VLD2008-143
VLD 2009-03-12
Okinawa   A memory-reduction method for multi-rate LDPC encoder
Wenming Tang, Xianghui WEI, Satoshi Goto (Waseda Univ.) VLD2008-144
 [more] VLD2008-144
VLD 2009-03-12
Okinawa   Emulation of Sequential Circuits by a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs)
and a programmable in... [more]
 Results 1 - 20 of 43  /  [Next]  
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