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Technical Committee on Reconfigurable Systems (RECONF)  (2009)

Chair: Yuichiro Shibata (Nagasaki Univ.) Vice Chair: Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary: Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)
Assistant: Hiroki Nakahara (Tokyo Inst. of Tech.), Yukitaka Takemura (INTEL)

Search Results: Keywords 'from:2010-01-26 to:2010-01-26'

[Go to Official RECONF Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 30  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
09:00
Kanagawa Keio Univ (Hiyoshi Campus) A study of software development environment for dynamic-reconfigurable processor MuCCRA-3.
Kazuei Hironaka, Katsunobu Nishimura (Tokai Univ.), Hideharu Amano (Keio Univ.) VLD2009-69 CPSY2009-51 RECONF2009-54
The dynamic-reconfigurable processor is consisted of many small and simple processing units. This processor is
able to ... [more]
VLD2009-69 CPSY2009-51 RECONF2009-54
pp.1-6
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
09:25
Kanagawa Keio Univ (Hiyoshi Campus) Reducing scheduling overheads in Dynamically Reconfigurable Processors
Ratna Krishnamoorthy (Univ of Tokyo), Keshavan Varadarajan, Mythri Alle (IISc), Ranjani Narayan (Morphing Machines), Masahiro Fujita (Univ of Tokyo), S K Nandy (IISc) VLD2009-70 CPSY2009-52 RECONF2009-55
 [more] VLD2009-70 CPSY2009-52 RECONF2009-55
pp.7-12
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
09:50
Kanagawa Keio Univ (Hiyoshi Campus) Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.), Dai Araki (InterDesign Technologies, Inc.) VLD2009-71 CPSY2009-53 RECONF2009-56
In this research , we proposed an effective hardware/software partitioning methodology based on C description with consi... [more] VLD2009-71 CPSY2009-53 RECONF2009-56
pp.13-18
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
10:15
Kanagawa Keio Univ (Hiyoshi Campus) Evaluation using Applications for RC-OS which supports Reconfigurable Computer System
Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ) VLD2009-72 CPSY2009-54 RECONF2009-57
FPGAs which allow users to create arbitrary logic circuits are used for speedup of the processing in many fields. We hav... [more] VLD2009-72 CPSY2009-54 RECONF2009-57
pp.19-24
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
10:50
Kanagawa Keio Univ (Hiyoshi Campus) A network deliverable hw/sw complex, video codec
Ryosuke Kurogi, Kentaro Hanai, Hakaru Tamukoh, Yuuichi Kobayashi, Masatoshi Sekine (Tokyo Univ. of Agr and Tech.) VLD2009-73 CPSY2009-55 RECONF2009-58
We propose a networked virtual circuit delivery system using the reconfigurability of FPGA.
The proposed system has a f... [more]
VLD2009-73 CPSY2009-55 RECONF2009-58
pp.25-30
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
11:15
Kanagawa Keio Univ (Hiyoshi Campus) Development of Interdisciplinary Research Environment by Collaboration of e-Learning and Remote FPGA
Jaeseong Kim, Shingo Yoshizawa, Yusaku Kaneta, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.) VLD2009-74 CPSY2009-56 RECONF2009-59
Field programmable gate array (FPGA) can reconfigure logic circuits after production, which is embedded into electric in... [more] VLD2009-74 CPSY2009-56 RECONF2009-59
pp.31-34
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
13:05
Kanagawa Keio Univ (Hiyoshi Campus) FPGA Implementation of Discrete Wavlet Transform Using Impulse C
Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.) VLD2009-75 CPSY2009-57 RECONF2009-60
Discrete Wavelet Transform(DWT), that is used for Image compression on JPEG2000, makes theoreticallyless noises than Dis... [more] VLD2009-75 CPSY2009-57 RECONF2009-60
pp.35-40
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
13:30
Kanagawa Keio Univ (Hiyoshi Campus) An FPGA Implementation of Array Processor Performing 3D-DCT Effectively
Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu) VLD2009-76 CPSY2009-58 RECONF2009-61
Ordinary array processors randomly access to input-/coefficient-data in external memories many times during the 3D-DCT, ... [more] VLD2009-76 CPSY2009-58 RECONF2009-61
pp.41-46
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
13:55
Kanagawa Keio Univ (Hiyoshi Campus) Computer Aided Detection System Implementation for recognize cancer in Mammograms over a FPGA
Yessica Suarez Henandez (IPN/Univ. of Electro-Comm.), Sayaka Akioka, Tsutomu Yoshinaga, Volodymyr Ponomaryov, Gonzalo Duchen Sanchez (Univ. of Electro-Comm.) VLD2009-77 CPSY2009-59 RECONF2009-62
A Computer Aided Detection, CAD, system was implemented using a FPGA development board to recognize cancer in Mammogram.... [more] VLD2009-77 CPSY2009-59 RECONF2009-62
pp.47-52
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
14:30
Kanagawa Keio Univ (Hiyoshi Campus) A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure
Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani (Tokyo Univ.), Hideharu Amano (Keio Univ.) VLD2009-78 CPSY2009-60 RECONF2009-63
We propose a non-minimal fully adaptive routing methodology
which does not require the use of virtual channels for its
... [more]
VLD2009-78 CPSY2009-60 RECONF2009-63
pp.53-58
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
14:55
Kanagawa Keio Univ (Hiyoshi Campus) Design of Reconfigurable Logic Device based on Variable Grain Logic Cell
Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-79 CPSY2009-61 RECONF2009-64
We propose a variable grain logic cell(VGLC)architecture. Its key feature is variable granularity which helps to create ... [more] VLD2009-79 CPSY2009-61 RECONF2009-64
pp.59-64
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
15:55
Kanagawa Keio Univ (Hiyoshi Campus) Residue-Binary Conversion Using Signed-Digit Number Arithmetic
Changjun Jiang, Shugang Wei (Gunma Univ.) VLD2009-80 CPSY2009-62 RECONF2009-65
By introducing a signed-digit(SD) number arithmetic into a residue number system (RNS), arithmetic operations can be per... [more] VLD2009-80 CPSY2009-62 RECONF2009-65
pp.71-76
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
16:20
Kanagawa Keio Univ (Hiyoshi Campus) Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation
Mingda Zhang, Shugang Wei (Gunma Univ.) VLD2009-81 CPSY2009-63 RECONF2009-66
 [more] VLD2009-81 CPSY2009-63 RECONF2009-66
pp.77-82
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
16:45
Kanagawa Keio Univ (Hiyoshi Campus) Hardware Specialization of Digital Filters for Vibration Control
Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (Toyohashi Univ. of Tech.) VLD2009-82 CPSY2009-64 RECONF2009-67
The logic circuit can generally be reduced, if any input of the circuit is given as a constant. The derived circuit
mig... [more]
VLD2009-82 CPSY2009-64 RECONF2009-67
pp.83-88
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-26
17:10
Kanagawa Keio Univ (Hiyoshi Campus) A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching
Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-83 CPSY2009-65 RECONF2009-68
Requirement for application-specific processor is really increasing recently, however, it takes much time to design a pr... [more] VLD2009-83 CPSY2009-65 RECONF2009-68
pp.89-94
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
09:00
Kanagawa Keio Univ (Hiyoshi Campus) Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) VLD2009-84 CPSY2009-66 RECONF2009-69
This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each log... [more] VLD2009-84 CPSY2009-66 RECONF2009-69
pp.95-99
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
09:25
Kanagawa Keio Univ (Hiyoshi Campus) Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array
Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2009-85 CPSY2009-67 RECONF2009-70
 [more] VLD2009-85 CPSY2009-67 RECONF2009-70
pp.101-106
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
10:00
Kanagawa Keio Univ (Hiyoshi Campus) Granularity Optimization Method for AES Encryption Implementation on CUDA
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA) VLD2009-86 CPSY2009-68 RECONF2009-71
GPGPU as parallel computation platform has been noticed from almost all reseach fields. In particular CUDA occupie... [more] VLD2009-86 CPSY2009-68 RECONF2009-71
pp.107-112
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
10:25
Kanagawa Keio Univ (Hiyoshi Campus) Effective Hardware Task Context Switching in Virtex-4 FPGAs
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2009-87 CPSY2009-69 RECONF2009-72
A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic... [more] VLD2009-87 CPSY2009-69 RECONF2009-72
pp.113-118
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
10:50
Kanagawa Keio Univ (Hiyoshi Campus) Hardware Acceleration in a Scalable FPGA System
Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-88 CPSY2009-70 RECONF2009-73
Currently, FPGAs are utilized for hardware experiments or practices in many educational institutes.
In a field of high ... [more]
VLD2009-88 CPSY2009-70 RECONF2009-73
pp.119-124
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