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Technical Committee on Dependable Computing (DC)  (2019)

Chair: Hiroshi Takahashi (Ehime Univ.) Vice Chair: Tatsuhiro Tsuchiya (Osaka Univ.)
Secretary: Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Search Results: Keywords 'from:2020-02-26 to:2020-02-26'

[Go to Official DC Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2020-02-26
10:00
Tokyo   On Machine Learning Based Accuracy Improvement for A Digital Temperature and Voltage Sensor
Masayuki Gondo, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2019-86
To measure an on-chip temperature and voltage during VLSI operation, an RO(Ring Oscillator)-based digital temperature an... [more] DC2019-86
pp.1-6
DC 2020-02-26
10:25
Tokyo   Defective Chip Prediction Modeling Using Convolutional Neural Networks
Ryunosuke Oka, Satoshi Ohtake (Oita Univ.), Kouichi Kumaki (Renesas) DC2019-87
In recent years, the cost of LSI testing which guarantees reliability has relatively increased due to the development of... [more] DC2019-87
pp.7-12
DC 2020-02-26
10:50
Tokyo   A study on temperature dependence on discrimination of resistive opens using machine learning-based anomaly detection
Ryotaroh Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2019-88
 [more] DC2019-88
pp.13-18
DC 2020-02-26
11:35
Tokyo   Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing
Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Youichi Maeda, Jun Matsushima (Renesas) DC2019-89
For guaranteeing the functional safety of an in-vehicle system, a power-on self-test (POST) is required to test the devi... [more] DC2019-89
pp.19-24
DC 2020-02-26
12:00
Tokyo   A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs
Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2019-90
With the complexity for VLSIs, transition fault testing is required. However, VLSIs generally have more untestable trans... [more] DC2019-90
pp.25-30
DC 2020-02-26
12:25
Tokyo   Glitch PUF utilizing Unrolled Architecture and its Evaluation
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) DC2019-91
The physically unclonable functions (PUFs) have attracted attention as technologies for authentication of large scale in... [more] DC2019-91
pp.31-36
DC 2020-02-26
14:10
Tokyo   A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT
Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2019-92
Recently, in at-speed scan testing, excessive capture power dissipation is a serious problem. Low capture power test gen... [more] DC2019-92
pp.37-42
DC 2020-02-26
14:35
Tokyo   Power Analysis for Logic Area of LSI Including Memory Area
Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-93
Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting... [more] DC2019-93
pp.43-48
DC 2020-02-26
15:00
Tokyo   Improving Controllability of Signal Transitions in the High Switching Area of LSI
Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] DC2019-94
pp.49-54
DC 2020-02-26
15:45
Tokyo   Frequency Variation of Ring Oscillators During Long-Time Operation on FPGA
Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-95
FPGAs (Field Programmable Gate Arrays) are integrated circuits that can be implemented arbitrary logic functions by reco... [more] DC2019-95
pp.55-60
DC 2020-02-26
16:10
Tokyo   Accurate Recycled FPGA Detection Based on Exhaustive Path Analysis
Michihiro Shintani, Foisal Ahmed, Michiko Inoue (NAIST) DC2019-96
 [more] DC2019-96
pp.61-66
DC 2020-02-26
16:35
Tokyo   Soft Error Tolerance of Power-Supply-Noise Hardened Latches
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-97
In recent years, with the scaling down and low-power operation of VLSI circuits, reliability degradation due to soft err... [more] DC2019-97
pp.67-72
 Results 1 - 12 of 12  /   
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