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Technical Committee on Component Parts and Materials (CPM)  (2006)

Chair: Mayumi Takeyama (Kitami Inst. of Tech.) Vice Chair: Yuichi Nakamura (Toyohashi Univ. of Tech.)
Secretary: Hideki Nakazawa (Hirosaki Univ.)
Assistant: Yasuo Kimura (Tokyo Univ. of Tech.), Tomoaki Terasako (Ehime Univ.), Fumihiko Hirose (Yamagata Univ.)

Search Results: Keywords 'from:2007-01-18 to:2007-01-18'

[Go to Official CPM Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 26  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, CPM 2007-01-18
09:00
Tokyo Kika-Shinko-Kaikan Bldg. On-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation
Takumi Danjo, Daisuke Kosaka, Makoto Nagata (Kobe Univ.)
 [more] CPM2006-129 ICD2006-171
pp.1-5
ICD, CPM 2007-01-18
09:25
Tokyo Kika-Shinko-Kaikan Bldg. Study on Active Substrate Noise Cancelling Technique using Power Line di/dt Detector
Taisuke Kazama (Univ. of Tokyo), Makoto Ikeda, Kunihiro Asada (VDEC)
 [more] CPM2006-130 ICD2006-172
pp.7-12
ICD, CPM 2007-01-18
09:50
Tokyo Kika-Shinko-Kaikan Bldg. Measurement of Delay Variation Due to Inductive Coupling Noise in 90nm Global Interconnects
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
Inductive coupling is becoming a design concern for global interconnects in nano-meter technologies. This paper shows me... [more] CPM2006-131 ICD2006-173
pp.13-18
ICD, CPM 2007-01-18
10:15
Tokyo Kika-Shinko-Kaikan Bldg. Measurement of Delay Degradation Due to Power Supply Noise and Delay Variation Estimation with Full-Chip Simulation
Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. Tech.), Takao Onoye (Osaka Univ.)
Power integrity is an crucial design issue in nano-meter technologies because of lowered supply voltage and current incr... [more] CPM2006-132 ICD2006-174
pp.19-23
ICD, CPM 2007-01-18
10:55
Tokyo Kika-Shinko-Kaikan Bldg. Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform
Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.)
Delay variability due to dynamic power supply noise is elucidated by on-chip signal waveform measurements at 100-ps/100-... [more] CPM2006-133 ICD2006-175
pp.25-29
ICD, CPM 2007-01-18
11:20
Tokyo Kika-Shinko-Kaikan Bldg. [Special Invited Talk] Proximity Inter-chip Communications
Tadahiro Kuroda, Kiichi Niitsu (Keio Univ.)
 [more] CPM2006-134 ICD2006-176
pp.31-35
ICD, CPM 2007-01-18
13:00
Tokyo Kika-Shinko-Kaikan Bldg. [Invited Talk] Fine electronic cuircuit pattern formation by various metal nanoparticle pastes -- Approach by the design of metal nanoparticles --
Masami Nakamoto (Osaka Munic. Tech. Res. Inst.)
 [more] CPM2006-135 ICD2006-177
pp.37-42
ICD, CPM 2007-01-18
13:50
Tokyo Kika-Shinko-Kaikan Bldg. “In Situ” Evaluation for On-Chip Inductors Using Impedance Balance Method
Mizuki Motoyoshi, Minoru Fujishima (The Univ. of Tokyo)
 [more] CPM2006-136 ICD2006-178
pp.43-48
ICD, CPM 2007-01-18
14:15
Tokyo Kika-Shinko-Kaikan Bldg. Design of Wideband tuning VCO for TV Receiver System
Takatsugu Kamata, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.)
 [more] CPM2006-137 ICD2006-179
pp.49-54
ICD, CPM 2007-01-18
14:40
Tokyo Kika-Shinko-Kaikan Bldg. An Integrated 20-26 GHz CMOS Up-Conversion Mixer with Low Power Consumption
Yuki Kambayashi, Ivan Chee Hong Lai, Minoru Fujishima (U.T.)
A fully integrated 20-26 GHz broadband up-conversion mixer with low power consumption is demonstrated on 90nm CMOS techn... [more] CPM2006-138 ICD2006-180
pp.55-60
ICD, CPM 2007-01-18
15:20
Tokyo Kika-Shinko-Kaikan Bldg. [Special Invited Talk] 3-Dimensional Packaging Technology and Super-Chip Integration
Tetsu Tanaka, Takafumi Fukushima, Mitsumasa Koyanagi (Tohoku Univ.)
 [more] CPM2006-139 ICD2006-181
pp.61-65
ICD, CPM 2007-01-18
16:35
Tokyo Kika-Shinko-Kaikan Bldg. Local deformation and residual stress of thin chips stacked by flip chip structures
Hideo Miura, Nobuki Ueta, Yuki Sato (Tohoku Univ.)
 [more] CPM2006-140 ICD2006-182
pp.67-72
ICD, CPM 2007-01-19
09:00
Tokyo Kika-Shinko-Kaikan Bldg. Development of Packages for Ultra-violet Light-Emitting Diodes -- Approach to high-light-extraction efficiency by Flip-Chip packages --
Iwao Mitsuishi, Shinya Nunoue, Hiroshi Yamada, Shinya Nunoue (Toshiba)
 [more] CPM2006-141 ICD2006-183
pp.73-76
ICD, CPM 2007-01-19
09:25
Tokyo Kika-Shinko-Kaikan Bldg. Ultra-Fine Pitch Cu Bumpless Interconnect for High Density System Integration
Aktisu Shigetou, Toshihiro Itoh, Tadatomo Suga (Univ. of Tokyo)
We report the studies on the ultra-fine pitch Cu bumpless interconnect relating to the direct bonding of CMP-Cu done by ... [more] CPM2006-142 ICD2006-184
pp.77-81
ICD, CPM 2007-01-19
09:50
Tokyo Kika-Shinko-Kaikan Bldg. Modeling of Wire Bonding Process for High Performance Device
Eiichi Yamada, Masazumi Amagai (TI Japan)
 [more] CPM2006-143 ICD2006-185
pp.83-86
ICD, CPM 2007-01-19
10:15
Tokyo Kika-Shinko-Kaikan Bldg. Signal Transmission Guideline in IC Package
Kentaro Takao, Chikara Azuma, Masazumi Amagai (TIJ)
 [more] CPM2006-144 ICD2006-186
pp.87-90
ICD, CPM 2007-01-19
10:55
Tokyo Kika-Shinko-Kaikan Bldg. Failure analysis system to classify failure modes using combination of FBMs
Hitoshi Maeda, Fumihito Ohta, Michio Kuniya, Koji Fukumoto (Renesas Technology)
 [more] CPM2006-145 ICD2006-187
pp.91-96
ICD, CPM 2007-01-19
11:20
Tokyo Kika-Shinko-Kaikan Bldg. Improvement of layout analysis by connecting emission/OBIRCH analysis with CAD data
Akira Shimase, Akihito Uchikado, Mitsuaki Saeki, Shinichi Watarai, Takeshi Suzuki, Toshiyuki Majima (Renesas), Kazuhiro Hotta, Hirotoshi Terada (HPK)
 [more] CPM2006-146 ICD2006-188
pp.97-102
ICD, CPM 2007-01-19
11:45
Tokyo Kika-Shinko-Kaikan Bldg. SoC macro-block diagnosis using extracted layout information
Katsuyoshi Miura, Koji Nakamae (Osaka Univ.)
A SoC macro-block diagnostic method using a netlist extracted from layout data is proposed. A hard IP core that does no... [more] CPM2006-147 ICD2006-189
pp.103-108
ICD, CPM 2007-01-19
13:00
Tokyo Kika-Shinko-Kaikan Bldg. A Constrained Test Generation Method for Low Power Testing
Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T)
High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] CPM2006-148 ICD2006-190
pp.109-114
 Results 1 - 20 of 26  /  [Next]  
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