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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-23
Kanagawa Hiyoshi Campus, Keio Univ. Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes
Kousuke Tada, Naoto Kawahara, Masato Yoshimi, Celimuge, Wu., Tsutomu Yoshinaga (UEC) VLD2016-76 CPSY2016-112 RECONF2016-57
This paper proposes an FPGA-based Handshake join acceleration using multiple-FPGA boards.
The proposed multi-node exten... [more]
VLD2016-76 CPSY2016-112 RECONF2016-57
(Joint) [detail]
Nagasaki Fukue Bunka Hall/Rodou Fukushi Center Design Evaluation of Low-Latency Handshake Join on FPGA
Masato Yoshimi, Yasin Oge, Celimuge Wu, Tsutomu Yoshinaga (UEC) CPSY2015-155 DC2015-109
This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementati... [more] CPSY2015-155 DC2015-109
RECONF 2013-09-18
Ishikawa Japan Advanced Institute of Science and Technology An Implementation of High Performance Stream Processing on a Reconfigurable Hardware
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Taro Fujii, Koichiro Furuta (Renesas Electronics), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-21
Stream processing is one of the applications that reconfigurable hardware can be highly effective. In this paper, we giv... [more] RECONF2013-21
IN 2013-06-20
Fukui University of Fukui, Bunkyo Campus, Memorial Academy Hall Writing Window Join Processor in C
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) IN2013-26
In the past, there has always been a wide gap between the skills for designing software and hardware. Now that reconfigu... [more] IN2013-26
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
Kanagawa Keio Univ (Hiyoshi Campus) A Consideration of Window Join Operator over Data Streams by using FPGA
Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC) VLD2010-111 CPSY2010-66 RECONF2010-80
An implementation technique of window join operator by using FPGA is studied in order to improve the performance. Window... [more] VLD2010-111 CPSY2010-66 RECONF2010-80
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