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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-03-01
11:15		 Okinawa Okinawa Ken Seinen Kaikan Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs
Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2018-125 HWS2018-88		 This article presents a method for synthesizing circuits with distributed control from CDFGs (control data flow graphs).... [more] VLD2018-125 HWS2018-88
pp.193-198
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-25
09:25		 Kanagawa Hiyoshi Campus, Keio Univ. Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit
Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH) VLD2016-95 CPSY2016-131 RECONF2016-76		 When variable latency for digital circuits are assumed, circuits can work with a small clock period that
has the possib... [more]		 VLD2016-95 CPSY2016-131 RECONF2016-76
pp.165-170
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
09:45		 Nagasaki Nagasaki Kinro Fukushi Kaikan Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs
Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-61 DC2015-57		 This paper proposes an extension of distributed control, which enables efficient run-time scheduling of variable latency... [more] VLD2015-61 DC2015-57
pp.153-158
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
17:05		 Oita B-ConPlaza Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis
Junghoon Oh, Mineo Kaneko (JAIST) VLD2014-90 DC2014-44		 As the device size decreases, the reliability degradation caused by soft-errors becomes one of the greatest issues in cu... [more] VLD2014-90 DC2014-44
pp.129-134
 Results 1 - 4 of 4  /   
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