IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 18 of 18  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2023-02-28
13:25
Tokyo Kikai-Shinko-Kaikan Bldg
(Primary: On-site, Secondary: Online)
A Clear and Understandable Notation for Expressing T-Way Test Sequence Generation Constraints
Lele Jiang, Tatsuhiro Tsuchiya (Osaka Univ.) DC2022-85
This paper focuses on the problem of constraint representation for the generation of t-way test sequences.
T-way seque... [more]
DC2022-85
pp.16-20
DC 2018-02-20
11:40
Tokyo Kikai-Shinko-Kaikan Bldg. A test generation method based on k-cycle testing for finite state machines
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81
Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] DC2017-81
pp.25-30
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:50
Kumamoto Kumamoto-Kenminkouryukan Parea On low power oriented test pattern compaction using SAT solver
Yusuke Matsunaga (Kyushu Univ.) VLD2017-43 DC2017-49
This paper proposes a test pattern compaction method under power
consumption constraint, which uses SAT solver based ... [more]
VLD2017-43 DC2017-49
pp.95-99
SS, DC 2017-10-20
09:30
Kochi Kochi City Culture-plaza CUL-PORT On the generation of constrained locating arrays using an SMT solver
Hao Jin (Osaka Univ.), Eun-Hye Choi (AIST), Tatsuhiro Tsuchiya (Osaka Univ.) SS2017-30 DC2017-29
Combinatorial interaction testing (CIT) is a well-known testing strategy for software systems. We inves-
tigate a new C... [more]
SS2017-30 DC2017-29
pp.55-60
SIP, CAS, MSS, VLD 2017-06-20
14:50
Niigata Niigata University, Ikarashi Campus SAT model sampling for test pattern generation considering signal transition activities
Yusuke Matsunaga (Kyushu Univ.) CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21
This paper presents a test pattern generation method with considering
signal transition activities using a SAT solver... [more]
CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21
pp.107-112
KBSE 2016-05-27
10:00
Tokyo Doshisha Univ. Tokyo Branch Office Reducing the number of mutants with equivalent bug detection ability
Tomohiro Ueno, Hirohide Haga (Doshisha Univ.) KBSE2016-5
Mutation analysis is a method to evaluate the software test cases set quality. In mutation analysis, mutant programs are... [more] KBSE2016-5
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
13:50
Nagasaki Nagasaki Kinro Fukushi Kaikan Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories
Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) VLD2015-40 DC2015-36
The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memor... [more] VLD2015-40 DC2015-36
pp.19-24
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan An approach to LFSR/MISR seed generation for delay fault BIST
Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66
In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST.
A widely used conventional way to... [more]
VLD2015-70 DC2015-66
pp.213-218
DC 2015-06-16
16:25
Tokyo Kikai-Shinko-Kaikan Bldg. Using binary decision diagrams for constraint handling in test case generation
Tatsuhiro Tsuchiya (Osaka Univ.) DC2015-21
This paper discusses constraint handling in test case generation for Combinatorial Interaction Testing (CIT). CIT requir... [more] DC2015-21
pp.31-34
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
09:40
Oita B-ConPlaza A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors
Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) VLD2014-98 DC2014-52
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] VLD2014-98 DC2014-52
pp.179-184
DC 2014-06-20
16:25
Tokyo Kikai-Shinko-Kaikan Bldg. An evaluation for Testability of Functional k-Time Expansion Models
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation
m... [more]
DC2014-17
pp.45-50
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
08:55
Kagoshima   A Method of LFSR Seed Generation for Delay Fault BIST
Taro Honda, Satoshi Ohtake (Oita Univ.) VLD2013-92 DC2013-58
In this paper, we propose a method to generate LFSR seeds for delay fault BIST. A conventional way to generate seeds is ... [more] VLD2013-92 DC2013-58
pp.227-231
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
09:45
Kagoshima   A Method of High Quality Transition Test Generation Using RTL Information
Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] VLD2013-94 DC2013-60
pp.239-244
SS, IPSJ-SE 2013-10-25
13:30
Ishikawa   Efficient random test case generation for constrained interaction testing
Yasuhiro Hirasaki, Hideharu Kojima, Tatsuhiro Tsuchiya (Osaka Univ.) SS2013-45
This paper discusses interaction testing using random testing.
Random testing can generate test cases very fast, but d... [more]
SS2013-45
pp.163-166
DC 2013-06-21
14:15
Tokyo Kikai-Shinko-Kaikan Bldg. A method of deterministic LFSR seed generation for scan-based BIST
Takanori Moriyasu, Satoshi Ohtake (Oita Univ.) DC2013-11
This paper proposes a method of LFSR seed generation for LFSR reseeding of scan-based BIST of VLSI circuits. So far, a s... [more] DC2013-11
pp.7-12
SS 2013-01-10
16:00
Okinawa   On the Probability of Interaction Fault Detection Using Random Testing in the Presence of Constraints on Parameter Values
Daiki Shigeoka, Hideharu Kojima, Tatsuhiro Tsuchiya (Osaka Univ.)
This paper discusses random testing, which is a simple approach to test case generation for software testing. A notable ... [more] SS2012-51
pp.31-35
DC 2008-02-08
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. A Test Generation Methods for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint
Ryoichi Inoue, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) DC2007-78
We proposed a fault-independent test generation method for logical fault testing of state-observable FSMs and a fault-de... [more] DC2007-78
pp.69-76
VLD, IPSJ-SLDM 2006-05-12
11:15
Ehime Ehime University Power-Conscious Microprocessor-Based Testing of System-on-Chip
Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST)
In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and resp... [more] VLD2006-10
pp.25-30
 Results 1 - 18 of 18  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan