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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-ARC [detail] | 2022-10-12 14:00 |
Niigata | Yuzawa Toei Hotel (Primary: On-site, Secondary: Online) |
A Don't Care Filling Algorithm of Control Signals for Concurrent Testing Xu Haofeng, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (KSU), Arai Masayuki (Nihon Univ.)  CPSY2022-24 DC2022-24 |
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] | CPSY2022-24 DC2022-24 pp.37-42 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 11:00 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3 |
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] | CPSY2022-3 DC2022-3 pp.13-18 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 10:30 |
Online | Online | A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90 |
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] | CPSY2021-56 DC2021-90 pp.67-72 |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 15:45 |
Online | Online | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12 |
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] | CPSY2020-12 DC2020-12 pp.75-80 |
| DC | 2019-02-27 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Compaction Method for Test Sensitization State in Controllers Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80 |
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] | DC2018-80 pp.55-60 |
| DC | 2018-02-20 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78 |
It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] | DC2017-78 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] | VLD2017-37 DC2017-43 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | On low power oriented test pattern compaction using SAT solver Yusuke Matsunaga (Kyushu Univ.) VLD2017-43 DC2017-49 |
This paper proposes a test pattern compaction method under power consumption constraint, which uses SAT solver based ... [more] |
VLD2017-43 DC2017-49 pp.95-99 |
| DC | 2017-02-21 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A dynamic test compaction method on low power oriented test generation using capture safe test vectors Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ.) DC2016-74 |
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] | DC2016-74 pp.1-6 |
| MSS, CAS, SIP, VLD | 2015-06-17 11:10 |
Hokkaido | Otaru University of Commerce | Accelerating techniques for test pattern compaction for large circuits Yusuke Matsunaga (Kyushu Univ.) CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5 |
This paper presents accelerating techniques for test pattern compaction algorithm applicable for large scale circuits.... [more] |
CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Study on Test Generation for Effective Test Compaction Yukino Kusuyama, Tatuya Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) VLD2012-105 DC2012-71 |
In recent year, the numbers of target fault models and faults for testing increase because the number of gates on VLSIs ... [more] | VLD2012-105 DC2012-71 pp.267-272 |
| DC | 2012-02-13 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A method to reduce the number of test patterns for transition faults using control point insertions Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) DC2011-82 |
In recent year, the growing density and complexity for VLSIs cause an increase in the number of test patterns. Moreover,... [more] | DC2011-82 pp.37-42 |
| DC | 2010-02-15 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Compaction Oriented Control Point Insertion Method for Transition Faults Yoshitaka Yumoto, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.) DC2009-72 |
The recent advances in semiconductor processing technology have resulted in the exponential increase in LSI circuit dens... [more] | DC2009-72 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 13:25 |
Kochi | Kochi City Culture-Plaza | A Test Compaction Oriented Don't Care Identification Method Motohiro Wakazono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) VLD2009-62 DC2009-49 |
In recent year, the growing density and complexity for VLSIs cause an increase in the number of test pattern and an incr... [more] | VLD2009-62 DC2009-49 pp.149-154 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 10:20 |
Fukuoka | Kitakyushu International Conference Center | A Note on Expansion of Convolutional Compactors on Galois Field Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
Convolutional compactors offer a promising technique of compacting test responses. In this study we expand the architect... [more] | VLD2005-78 ICD2005-173 DC2005-55 pp.13-18 |
| ICD, CPM | 2005-09-08 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Diagnostic Test Compaction for Combinational and Sequential Circuits Yoshinobu Higami (Ehime Univ.), Kewal K Saluja (Univ. of Wisconsin), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ.) |
Recently, it is getting important to reduce the cost of test and fault diagnosis. Since the cost of test and fault diag... [more] |
CPM2005-89 ICD2005-99 pp.25-30 |
| ICD, CPM | 2005-01-28 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | On Finding Don't Cares in Test Sequences for Sequential Circuits and Applications to Test Compaction and Power Reduction Yoshinobu Higami (Ehime Univ.), Seiji Kajihara (Kyushu Inst. Tech.), Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ.) |
This paper presents a method for finding don't cares in test sequences hile keeping the original stuck-at fault coverage... [more] | CPM2004-169 ICD2004-214 pp.41-46 |
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