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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 13:15 |
Online | Online | A Study on Technology mapping method for Scalable Logic Module Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.)  VLD2021-68 CPSY2021-37 RECONF2021-76 |
The LUT (Lookup Table) , which is widely used as the logic cell in FPGA (Field Programmable Gate Array）, can implement a... [more] | VLD2021-68 CPSY2021-37 RECONF2021-76 pp.108-113 |
| HWS, VLD [detail] | 2020-03-04 11:20 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA Takashi Imagawa (Ritsumeikan Univ.), Yu Jaehoon (Tokyo Tech), Masanori Hashimoto (Osaka Univ.), Hiroyuki Ochi (Ritsumeikan Univ.) VLD2019-98 HWS2019-71 |
Via-Switch FPGAs have different features from conventional SRAM-based FPGAs. It is necessary to build the application ci... [more] | VLD2019-98 HWS2019-71 pp.25-29 |
| HWS, VLD | 2019-02-27 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan | Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework Masataka Aoki, Yukihide Kohira (Univ. of Aizu) VLD2018-102 HWS2018-65 |
In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultane... [more] | VLD2018-102 HWS2018-65 pp.55-60 |
| SIP, CAS, MSS, VLD | 2017-06-19 11:00 |
Niigata | Niigata University, Ikarashi Campus | Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation Ryosuke Koike, Takashi Imagawa (Ritsumeikan Univ.), Roberto Yusi Omaki (Synthesis), Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5 |
In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Bloc... [more] | CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] | RECONF2016-45 pp.29-34 |
| RECONF | 2015-06-20 16:15 |
Kyoto | Kyoto University | A Technology Mapping Method for Scalable Logic Module Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-27 |
In order to implement logic functions, conventional field-programmable gate arrays (FPGAs) employs look-up tables (LUTs)... [more] | RECONF2015-27 pp.147-152 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 11:10 |
Oita | B-ConPlaza | Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu) VLD2014-83 DC2014-37 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2014-83 DC2014-37 pp.87-92 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:00 |
Hokkaido | Hokkaido University | Accelerating Boolean Matching of LUT-based Circuits using CEGAR method Yusuke Matsunaga (Kyushu Univ.) CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 |
This paper describes an accelerating technique for Boolean matching of LUT-based circuits, which is based on CEGAR (coun... [more] | CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 pp.201-206 |
| CPSY, DC | 2014-04-25 14:00 |
Tokyo | Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2 |
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] | CPSY2014-2 DC2014-2 pp.3-8 |
|
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 13:45 |
Kanagawa | Hiyoshi Campus, Keio University | On Boolean Matching of LUT-based Circuits Yusuke Matsunaga (Kyushu Univ.) VLD2013-127 CPSY2013-98 RECONF2013-81 |
This paper describes two speed-up techniques for Boolean matching of LUT-based circuits. One is one-hot encoding tec... [more] |
VLD2013-127 CPSY2013-98 RECONF2013-81 pp.149-154 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:00 |
Kagoshima | ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2013-49 |
In this paper, we propose an ILP-based method for simultaneous optimal technology mapping, placement and routing for pro... [more] | RECONF2013-49 pp.57-62 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | An ILP Formulation of Placement and Routing for PLDs Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) VLD2012-75 DC2012-41 |
In this paper, we formulate the simultaneous technology mapping, placement and routing problem for programmable gate a... [more] |
VLD2012-75 DC2012-41 pp.93-98 |
| NS, IN (Joint) |
2012-03-08 09:50 |
Miyazaki | Miyazaki Seagia | A proposal of redundant network architecture between cloud data centers Takaaki Koyama, Tomoko Inoue, Toshiharu Kishi, Yukio Nagafuchi, Hideo Kitazume (NTT) IN2011-145 |
There are two major cloud network architectures for data center. One is "Hop by Hop" model by openflow technology, the o... [more] | IN2011-145 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 15:40 |
Kochi | Kochi City Culture-Plaza | FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2009-68 DC2009-55 |
This paper presents a novel logic optimization technique to minimize the number of LUTs for the post-processing of LUT-b... [more] | VLD2009-68 DC2009-55 pp.185-190 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 14:10 |
Kanagawa | An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
This paper presents a top-down cut enumeration for depth-minimum technology mapping for LUT-based FPGAs. Enumerating all... [more] | VLD2008-101 CPSY2008-63 RECONF2008-65 pp.57-62 |
|
| RECONF | 2008-09-26 10:30 |
Okayama | Okayama Univ. | Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-33 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | RECONF2008-33 pp.63-68 |
| VLD, IPSJ-SLDM | 2006-05-11 14:30 |
Ehime | Ehime University | Dynamic Reconfigurable Wiring Architecture and Its Application to Hardware Mapping Shinji Kimura (Waseda Univ.) |
Reconfigurable architecture is one of key technologies to cope with bugs and the specification changes of systerm LSI. E... [more] | VLD2006-2 pp.7-12 |
| MSS | 2005-08-22 14:15 |
Aichi | Aichi Prefectural University | On Technology Roadmapping for Concurrent System Technology Naoshi Uchihira (Toshiba Corp.) |
Recently, technology roadmaps have been actively constructed by governments, industry segments, academic societies and c... [more] | CST2005-17 pp.19-23 |
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