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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-21 09:50 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
Non-stop microprocessor with MTJ-based non-volatile devices Shota Nakabeppu, Nobuyuki Yamasaki (Keio Univ.)  CPSY2023-39 DC2023-105 |
Today, various embedded systems, including automobiles, home appliances, robots, spacecraft, and sensor networks, suppor... [more] | CPSY2023-39 DC2023-105 pp.7-11 |
| VLD, IPSJ-SLDM | 2013-05-16 16:25 |
Fukuoka | Kitakyushu International Conference Center | SoC System Design Methodology with Fully-Coherent Cache Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10 |
As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the en... [more] | VLD2013-10 pp.73-78 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 13:50 |
Fukuoka | Kyushu University | Rapid SoC Prototyping Based on Virtual Multi-Processor Model Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2010-58 DC2010-25 |
To meet both high performance and high energy efficiency, System-on-Chip (SoC) has a heterogenous architec- ture includi... [more] | VLD2010-58 DC2010-25 pp.7-12 |
| ICD, SDM | 2007-08-23 11:35 |
Hokkaido | Kitami Institute of Technology | A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms Atsufumi Shibayama, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro (NEC) SDM2007-147 ICD2007-75 |
Methods for clock generation, distribution, and synchronization in system-on-chip (SOC) designs have become important is... [more] | SDM2007-147 ICD2007-75 pp.35-40 |
| RECONF | 2007-05-17 17:20 |
Ishikawa | Kanazawa Bunka Hall | A Discussion on a Router for embedded Programmable Logic matriX (ePLX) Naoki Okuno, Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.), Takenobu Iwao, Hirofumi Nakano, Yoshihiro Okuno, Kazutami Arimoto (Renesas) RECONF2007-9 |
We propose a fine-grained programmable logic architecture designed to be embedded in system-on-chips (SoCs) to enhance t... [more] | RECONF2007-9 pp.49-54 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 16:10 |
Fukuoka | Kitakyushu International Conference Center | Test Scheduling for SoCs with Built-In Self-Repairable Memory Cores Yusuke Fukuda, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
This paper presents a power-constrained test scheduling mehtod for SoCs with built-in self repairable memories which are... [more] | VLD2006-61 DC2006-48 pp.59-64 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 10:20 |
Fukuoka | Kitakyushu International Conference Center | Reconfigurable Wrapper Design for Multi Clock Domain Cores Under Power Constraints Yu Tanaka, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
This paper presents a re-configurable wrapper design for scan-designed multi-clock domain cores in system-on-chips. The ... [more] | VLD2005-63 ICD2005-158 DC2005-40 pp.13-18 |
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