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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Locating High Power Consuming Area by Branch and Reconvergence Topology Analysis for Logic Circuit Tomoya Yamashita, Kohei Miyase, Xiaoqing Wen (Kyutech)  DC2023-101 |
In recent years, there has been remarkable progress in the manufacturing technology of LSIs (Large Scale Integration). D... [more] | DC2023-101 pp.41-46 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 10:30 |
Online | Online | Power Analysis Based on Probability Calculation of Small Regions in LSI Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 |
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] | VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 pp.12-17 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2016-46 pp.35-40 |
| SDM | 2015-06-19 15:50 |
Aichi | VBL, Nagoya Univ. | Fully compatible resistive random access memory with amorphous InGaZnO based thin film transistor fabrication process Keisuke Kado, Mutsunori Uenuma, Kyouhei Nabesaka, Kriti Sharma, Haruka Yamazaki, Satoshi Urakawa, Mami Fujii, Yasuaki Ishikawa, Yukiharu Uraoka (NAIST) SDM2015-52 |
a-InGaZnO based non-volatile memories were fabricated as resistive random access memory (ReRAM) for use in System on Pan... [more] | SDM2015-52 pp.75-80 |
| DC | 2014-06-20 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A X-Filling Method for Low-Capture-Power Scan Test Generation Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-12 |
In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activ... [more] |
DC2014-12 pp.15-20 |
| NC, MBE (Joint) |
2014-03-18 14:10 |
Tokyo | Tamagawa University | Study on temporal strategies of event-related desynchronization during task-switching Hiroshi Yokoyama, Isao Nambu (Nagaoka Univ. of Tech.), Jun Izawa (NTT), Yasuhiro Wada (Nagaoka Univ. of Tech.) MBE2013-142 |
Mental process related to mental rotation task of hands is influenced by the physical states. It is suggested that menta... [more] | MBE2013-142 pp.151-156 |
| DC | 2014-02-10 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Suitable Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path Ryo Ogawa, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-82 |
The power consumption of Very Large Scale Integrated circuit (VLSI) testing is a significant problem. The VLSI should be... [more] | DC2013-82 pp.19-24 |
| RECONF | 2009-05-15 10:00 |
Fukui | A low-power clustering tool using both routability and activity for FPGAs Junya Eto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-10 |
Although FPGA(Field Programmable Gate Array) has high exibility, there is a problem that power consumption is larger tha... [more] | RECONF2009-10 pp.55-60 |
|
| VLD, IPSJ-SLDM | 2007-05-11 11:45 |
Kyoto | Kyodai Kaikan | On power-conscious approach for prefix graph synthesis Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) |
A prefix graph visualizes a global structure of a parallel prefix adder at technology independent level. Several approa... [more] |
VLD2007-12 pp.31-36 |
| ICD, VLD | 2006-03-09 10:05 |
Okinawa | An accurate static power analysis method which considers local switching activities Tatsuya Yamamoto, Yuu Yamashita, Katsuhiro Oshikawa, Masahiro Fukui (Rits) |
For the logic level power estimation, there are two types of algorithms, i.e. dynamic and static ones, conventionally. T... [more] | VLD2005-110 ICD2005-227 pp.13-18 |
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