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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2024-01-31 12:35 |
Tokyo | KIT Toranomon Graduate School (Primary: On-site, Secondary: Online) |
[Invited Talk]
Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs Hiroshi Oka, Hidehiro Asai, Takumi Inaba, Shunsuke Shitakata, Hitoshi Yui, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Takashi Nakayama, Takahiro Mori (AIST)  SDM2023-74 |
Toward large-scale quantum computers, cryogenic CMOS circuits have been developed to control and readout the qubits insi... [more] | SDM2023-74 pp.1-4 |
| NLP, CAS | 2023-10-06 14:50 |
Gifu | Work plaza Gifu | A Design and Evaluation of the Up/Down Counter Type PWM Adder Using the Subthreshold Region Gaku Abe, Andrino Robles Roberto, Takumi Nihei, Tomochika Harada (Yamagata Univ.) CAS2023-42 NLP2023-41 |
This paper presents the design and evaluation of a PWM adder circuit using up/down counters operating in the subthreshol... [more] | CAS2023-42 NLP2023-41 pp.53-57 |
| NLP, CAS | 2023-10-06 15:10 |
Gifu | Work plaza Gifu | A PWM/digital Converter for Improved Conversion Resolution using Frequency Multiplicator Zhang He, Andrino Robles Roberto, Tomochika Harada (Yamagata Univ.) CAS2023-43 NLP2023-42 |
For IoT (Internet of Things) devices, a reduction in power consumption is desired. To reduce power consumption, researc... [more] | CAS2023-43 NLP2023-42 pp.58-61 |
| CCS | 2023-03-26 10:55 |
Hokkaido | RUSUTSU RESORT | A Stochastic Memory for Ultralow-Power IoT Devices and its Subthreshold CMOS Circuit Implementation Seiya Muramatsu, Kohei Nishida, Kota Ando (Hokkaido Univ.), Megumi Akai-Kasaya (Osaka Univ./Hokkaido Univ.), Tetsuya Asai (Hokkaido Univ.) CCS2022-68 |
We propose a CMOS circuit implementation of a memory circuit for ultralow-power IoT devices based on stochastic computin... [more] | CCS2022-68 pp.31-35 |
| ICD, SDM, ITE-IST [detail] | 2022-08-08 14:15 |
Online | Evaluation of Steep Subthreshold Slope Device "Dual-gate type PN-body Tied SOI-FET" for Ultra-low Voltage Operation Haruki Yonezaki, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC) SDM2022-38 ICD2022-6 |
In this study, we report the first prototype results of a Steep SS "Dual-Gate (DG) PN-Body Tied (PNBT) SOI-FET" for extr... [more] | SDM2022-38 ICD2022-6 pp.17-20 |
|
| SDM, ICD, ITE-IST [detail] | 2018-08-07 15:00 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | A 0.6V 9bit PWM Differential Arithmetic Circuit Fumiya Kojima, Tomochika Harada (Yamagata Univ) SDM2018-32 ICD2018-19 |
In this paper, we design and evaluate the analog / PWM conversion circuit and the PWM differential arithmetic circuit wh... [more] | SDM2018-32 ICD2018-19 pp.35-40 |
| VLD, HWS (Joint) |
2018-03-02 09:00 |
Okinawa | Okinawa Seinen Kaikan | On-chip and ultra low current measurement circuit based on potentiostat method Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2017-119 |
We propose a current measurement circuit using on - chip high resistance by MOSFET. Due to advances in biosensing techno... [more] | VLD2017-119 pp.181-186 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 12:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | 2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.) VLD2016-46 DC2016-40 |
This report proposes L1L5-type 2-step charge pump circuit that is suitable for boosting efficiently the subthreshold inp... [more] | VLD2016-46 DC2016-40 pp.13-18 |
| ICD, SDM, ITE-IST [detail] | 2016-08-02 09:00 |
Osaka | Central Electric Club | [Invited Talk]
Soft Error Immunity of Ultra-Low Voltage SRAM Masanori Hashimoto (Osaka Univ.) SDM2016-54 ICD2016-22 |
This paper discusses soft error immunity of near-threshold/subthreshold SRAM. In terrestrial environment, high-energy ne... [more] | SDM2016-54 ICD2016-22 pp.53-58 |
| VLD | 2014-03-05 13:25 |
Okinawa | Okinawa Seinen Kaikan | Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161 |
Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] | VLD2013-161 pp.147-151 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
A Design of 0.5V Subthreshold Digital Phase Locked Loop using Simple Synchronization Unit. Kousuke Watanabe, Tomochika Harada (Yamagata Univ.) ICD2013-129 |
In this paper, we design and evaluate the 0.5V subthreshold DPLL circuit. Under synchronization, fine tuning operation i... [more] | ICD2013-129 pp.67-72 |
| ICD, ITE-IST | 2013-07-05 17:40 |
Hokkaido | San Refre Hakodate | Failure mode analysis for flip-flops at low voltages Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto (Kyouto Univ.), Hiroshi Tsutsui (Hokkaido Univ.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Sato (Kyouto Univ.) ICD2013-45 |
Towards the reducing power consumption, subthreshold circuit which operates at a low voltage below the threshold voltage... [more] | ICD2013-45 pp.129-134 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki | NewWelCity Miyazaki | [Invited Talk]
Ultra Low Voltage Subthreshold Circuit Design Masanori Hashimoto (Osaka Univ.) VLD2011-82 DC2011-58 |
Subthreshold circuits, which are drawing attention for ultra low-power applications, are reviewed in terms of power diss... [more] | VLD2011-82 DC2011-58 pp.173-178 |
| ICD, ITE-IST | 2011-07-21 09:55 |
Hiroshima | Hiroshima Institute of Technology | A Sense Amplifier with High Speed Pre-Charge Operation for Ultra-Low-Voltage SRAM Chotaro Masuda, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kove Univ.) ICD2011-22 |
We propose a current latch sense amplifier with a current-reuse technique (CLSA-w/CR). The CLSA-w/CR is capable of hig... [more] |
ICD2011-22 pp.7-12 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
A 0.5V Subthreshold CMOS Analog Amplifier with Sub-MHz Bandwidth Takashi Mori, Tomochika Harada, Koichi Matsushita, Sumio Okuyama (Yamagata Univ.) ICD2010-103 |
In this paper, we present an ultra-low voltage analog amplifier based on a folded cascode opamp using subthreshold opera... [more] | ICD2010-103 pp.49-53 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | An Offset Compensation Method Using Subthreshold CMOS Operational Amplifiers for Fully Differential Amplifiers Tomoki Iida, Tetsuya Asai, Yoshihito Amemiya, Eiichi Sano (Hokkaido Univ.) |
An offset compensation method for fully differential amplifiers is described. The method uses a feedback bias circuit co... [more] | |
| ICD, ITE-IST | 2010-07-23 09:15 |
Osaka | Josho Gakuen Osaka Center | Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply Tomochika Harada (Yamagata Univ.) ICD2010-30 |
[more] | ICD2010-30 pp.55-60 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
A nanowatt DA converter for subthreshold CMOS LSIs Kazuki Yamamoto, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2009-88 |
An ultra-low power digital-to-analog (DA) converter based on the technique of pulse-width-modulated DA conversion was pr... [more] | ICD2009-88 pp.59-64 |
| NLP | 2009-11-13 15:05 |
Kagoshima | The design of Izhikevich model silicon neuron circuit Yuji Nagamatsu, Takashi Kohno, Kazuyuki Aihara (Univ. of Tokyo.) NLP2009-109 |
Izhikevich model is a 2 variable differential equations that express neuron dynamics. In spite of simple form of equati... [more] | NLP2009-109 pp.155-160 |
|
| ICD, ITE-IST | 2009-10-02 17:50 |
Tokyo | CIC Tokyo (Tamachi) | Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2009-62 |
Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication pr... [more] | ICD2009-62 pp.165-170 |
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