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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2008-07-18
09:50		 Tokyo Kikai-Shinko-Kaikan Bldg. A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support
Koichi Nakayama, Ken-ichi Kawasaki, Tetsuyoshi Shiota, Atsuki Inoue (Fujitsu Lab.) SDM2008-141 ICD2008-51		 A sub-$\micro$s wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and... [more] SDM2008-141 ICD2008-51
pp.77-82
ICD 2005-12-16
09:50		 Kochi   A Low Dynamic Power and Low Leakage Power 90-nm CMOS Clock Driver
Suguru Nagayama, Tadayoshi Enomoto (Chuo Univ.) 		A technique, which can minimize not only an active power (Pat) and an stand-by power (Pst) but also a delay time (td) of... [more] ICD2005-194
pp.13-18
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