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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2018-02-20
11:40		 Tokyo Kikai-Shinko-Kaikan Bldg. A test generation method based on k-cycle testing for finite state machines
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81		 Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] DC2017-81
pp.25-30
DC 2017-02-21
14:25		 Tokyo Kikai-Shinko-Kaikan Bldg. An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States
Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79		 Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] DC2016-79
pp.29-34
DC 2016-06-20
15:15		 Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models
Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14		 A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] DC2016-14
pp.25-30
DC 2014-06-20
16:25		 Tokyo Kikai-Shinko-Kaikan Bldg. An evaluation for Testability of Functional k-Time Expansion Models
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17		 A test generation method using functional k-time expansion models for data paths was proposed. In the test generation
m... [more]		 DC2014-17
pp.45-50
RCS, SR, SRW
(Joint)		 2014-03-04
11:05		 Tokyo Waseda Univ. DC Electric Power Routing Model System Using 920 MHz Band Remote Wireless Control
Yuma Nogami, Akihiro Kobayashi, Yuichi Kado (Kyoto Inst. of Tech.), Mikio Yamasaki (NTT-F RI), Akira Matsumoto, Masato Kaga (NTT-F) SRW2013-49		 There are some problems about grids in Japan ; risk of destabilization because of disseminated a lot of distributed gene... [more] SRW2013-49
pp.31-35
DC 2013-06-21
13:45		 Tokyo Kikai-Shinko-Kaikan Bldg. A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10		 In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] DC2013-10
pp.1-6
DC 2011-02-14
14:10		 Tokyo Kikai-Shinko-Kaikan Bldg. A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models
Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-65		 Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral sy... [more] DC2010-65
pp.39-44
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-12-01
11:25		 Fukuoka Kyushu University A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43		 Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very ha... [more] VLD2010-76 DC2010-43
pp.143-148
DC 2010-02-15
11:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A binding method for testability based on resources sequential depth reduction
Takaaki Cho, Toshinori Hosokawa (Nihon Univ.) DC2009-70		 Behavioral descriptions are recently used for circuit designs on application specific fields. Behavioral synthesis is us... [more] DC2009-70
pp.31-38
DC 2009-02-16
10:25		 Tokyo   A test pattern generation method to reduce the number of detected untestable faults on scan testing
Masayoshi Yoshimura (Kyusyu Univ.), Hiroshi Ogawa (Nihon Univ.), Yusyo Omori (Fujitsu Microelectronics), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meizi Univ.) DC2008-69		 Scan testing is one of the most popular test method fo VLSIs. In this test, only information of the circuit structure is... [more] DC2008-69
pp.7-12
DC 2008-02-08
10:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Test Generation Method for Full Scan Circuit Using Multi Cycle Capture Test
Yusho Omori, Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Koji Yamazaki (Meiji Univ.) DC2007-70		 Currently, scan testing is one of the most popular test methods for VLSIs. In this testing, only information of the circ... [more] DC2007-70
pp.19-24
 Results 1 - 11 of 11  /   
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