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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)  VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| CS, CAS | 2020-02-27 11:45 |
Kumamoto | Detecting Resistive-Open Defects of Power TSVs in 3D-ICs Koutaro Hachiya (Teikyo Heisei Univ.), Atsushi Kurokawa (Hirosaki Univ.) CAS2019-104 CS2019-104 |
A method is proposed which detects resistive-open defects of power TSVs in PDNs by measuring resistance between power mi... [more] | CAS2019-104 CS2019-104 pp.37-41 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 14:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-42 DC2015-38 |
The effect of a resistive open results in small delay in an IC. It is difficult to test small delay since signal delay a... [more] | VLD2015-42 DC2015-38 pp.31-36 |
| DC | 2013-02-13 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84 |
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] | DC2012-84 pp.25-30 |
| DC | 2012-06-22 14:20 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | [Invited Talk]
Empirical study for signal integrity-defects Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. Tokushima) DC2012-12 |
We try to empirically study signal integrity-defects. In this study, we analyze the resistive open fault that causes th... [more] |
DC2012-12 pp.21-26 |
| DC | 2010-02-15 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Modeling resistive open faults and generating their tests Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2009-68 |
In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive ope... [more] | DC2009-68 pp.19-24 |
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