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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD | 2024-01-29 14:40 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
 VLD2023-85 RECONF2023-88 |
We are developing a signal processing ASIC designed to operate at extremely low temperatures with the goal of realizing ... [more] | VLD2023-85 RECONF2023-88 pp.31-34 |
| DC | 2023-02-28 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
A Test Generation Method to Distinguish Multiple Fault Pairs for Improvement of Fault Diagnosis Resolution Yuya Chida, Toshinori Hosokawa (NIhon Univ.), Koji Yamazaki (Meiji Univ.) DC2022-83 |
(To be available after the conference date) [more] | DC2022-83 pp.6-11 |
| DC | 2021-12-10 14:00 |
Kagawa | (Primary: On-site, Secondary: Online) |
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57 |
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] | DC2021-57 pp.13-18 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 11:20 |
Online | Online | A Don't Care Filling Method of Control Signals for Controllers to Enhance Fault Diagnosability at Register Transfer Level Kohei Tsuchibuchi, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ.) CPSY2020-62 DC2020-92 |
With the progress of semiconductor technology in recent years, fault analysis is important to improve the yield of VLSIs... [more] | CPSY2020-62 DC2020-92 pp.73-78 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 12:00 |
Online | Online | A Logic Locking Method Based on Anti-SAT at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94 |
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] | CPSY2020-64 DC2020-94 pp.85-90 |
| DC, SS | 2019-10-24 16:00 |
Kumamoto | Kumamoto Univ. | A Non-scan Online Test Based on Covering n-Time State Transition Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47 |
As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] | SS2019-19 DC2019-47 pp.37-42 |
| DC | 2019-02-27 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Compaction Method for Test Sensitization State in Controllers Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80 |
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] | DC2018-80 pp.55-60 |
| DC | 2018-02-20 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78 |
It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] | DC2017-78 pp.7-12 |
| DC | 2018-02-20 11:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A test generation method based on k-cycle testing for finite state machines Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81 |
Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] | DC2017-81 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] | VLD2017-37 DC2017-43 pp.61-66 |
| ET | 2017-03-10 13:10 |
Ehime | National Institute of Technology, Niihama College | Development and Trial Evaluation of CPU Simulator with Register-transfer level Micro-Operation Shinya Hara, Yoshiro Imai (Kagawa Univ.) ET2016-113 |
This paper proposes a new educational tool for Computer Architecture, which can provide simulation of assembly program c... [more] | ET2016-113 pp.111-116 |
| DC | 2016-02-17 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An RTL Test Point Insertion Method to Reduce the Number of Test Patterns Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU) DC2015-93 |
Test point insertion methods to reduce the number of test patterns have been proposed for test cost reduction of VLSIs. ... [more] | DC2015-93 pp.43-48 |
| DC | 2014-06-20 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Hierarchical Testability Using Results of Test Environment Generation Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-16 |
Hierarchical test generation methods using functional register-transfer level circuits have been proposed as efficient t... [more] | DC2014-16 pp.39-44 |
| VLD | 2012-03-06 15:05 |
Oita | B-con Plaza | High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2011-128 |
It is widely known that high-level synthesis technology can improve the design productivity dramatically by raising the ... [more] | VLD2011-128 pp.49-54 |
| VLD | 2012-03-06 15:55 |
Oita | B-con Plaza | Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-130 |
A circuit has many false paths on which signal transitions never affect its circuit behavior.This report proposes a logi... [more] | VLD2011-130 pp.61-66 |
| VLD, CAS, SIP | 2008-06-27 09:40 |
Hokkaido | Hokkaido Univ. | An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST) CAS2008-21 VLD2008-34 SIP2008-55 |
Information on false paths in a circuit is useful for design and test. The use of this information may contribute not o... [more] | CAS2008-21 VLD2008-34 SIP2008-55 pp.13-18 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 09:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-119 CPSY2007-62 RECONF2007-65 |
As device feature size decreases, interconnection delay becomes the dominating factor of total delay. In addition, as ... [more] |
VLD2007-119 CPSY2007-62 RECONF2007-65 pp.7-12 |
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