Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, DC, IPSJ-ARC [detail] |
2022-07-28 13:30 |
Yamaguchi |
Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] |
CPSY2022-8 DC2022-8 pp.41-46 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima |
Satellite Campus Hiroshima |
Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] |
RECONF2018-37 pp.15-20 |
DC |
2018-02-20 16:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87 |
MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to... [more] |
DC2017-87 pp.61-66 |
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2018-01-19 11:05 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68 |
This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] |
VLD2017-80 CPSY2017-124 RECONF2017-68 pp.107-112 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] |
RECONF2016-45 pp.29-34 |
ICD |
2013-04-12 08:30 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) |
[Invited Talk]
Complementary atom-switch based programmable cell array and its demostraion of logic mapping synthesized from RTL code Makoto Miyamura, Munehiro Tada, Toshitsugu Sakamoto, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (LEAP) ICD2013-12 |
Reconfigurable nonvolatile programmable-logic using complementary atom switch (CAS) is successfully demonstrated on a 65... [more] |
ICD2013-12 pp.55-59 |
RECONF |
2011-05-13 11:10 |
Hokkaido |
Hokkaido Univ. (Faculty of Eng., B3 Bldg.) |
Implementation and Evaluation of a low power accelerator SLD-2 Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16 |
Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] |
RECONF2011-16 pp.91-96 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 10:00 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems Tomonori Izumi (Ritsumeikan Univ.) VLD2010-101 CPSY2010-56 RECONF2010-70 |
Reconfigurable logic devices are expected to be key devices to implement real-time, low-power, small autonomous recognit... [more] |
VLD2010-101 CPSY2010-56 RECONF2010-70 pp.123-126 |
RECONF |
2010-09-17 09:25 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
COGRE: A Novel Compact Logic Cell Architecture for Area Reduction Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-31 |
In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) a... [more] |
RECONF2010-31 pp.79-84 |
RECONF |
2010-05-14 11:45 |
Nagasaki |
|
Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2010-14 |
Reconfigurable devices can be configured any logical hardware structures by users. Reconfigurable systems that have reco... [more] |
RECONF2010-14 pp.75-80 |
ED, SDM |
2010-02-23 11:00 |
Okinawa |
Okinawaken-Seinen-Kaikan |
Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network Yuta Shiratori, Kensuke Miura (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST) ED2009-208 SDM2009-205 |
We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon’s expansion of Boolean logic functio... [more] |
ED2009-208 SDM2009-205 pp.71-76 |
SCE |
2009-10-20 14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Dynamically Reconfigurable Single Flux Quantum Logic Gates Yuki Yamanashi, Ichiro Okawa, Nobuyuki Yoshikawa (Yokohama Nat. Univ.) SCE2009-20 |
Novel reconfigurable superconductive single flux quantum logic gates, the function of which can be dynamically defined b... [more] |
SCE2009-20 pp.19-23 |
SIS |
2009-03-05 15:45 |
Tokyo |
|
[Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs.
We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-30 15:10 |
Kanagawa |
|
A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] |
VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka |
Kitakyushu Science and Research Park |
A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] |
RECONF2008-42 pp.21-26 |
RECONF |
2008-09-26 10:30 |
Okayama |
Okayama Univ. |
Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-33 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] |
RECONF2008-33 pp.63-68 |
RECONF |
2008-05-22 16:05 |
Fukushima |
The University of Aizu |
A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] |
RECONF2008-8 pp.43-48 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka |
Kitakyushu International Conference Center |
A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33 |
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained
types, its structure can ... [more] |
RECONF2007-33 pp.7-12 |
RECONF |
2007-05-17 16:10 |
Ishikawa |
Kanazawa Bunka Hall |
Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-7 |
Reconfigurable logic devices are classified into two type of logic block, which are coarse-grain and fine-grain by the b... [more] |
RECONF2007-7 pp.37-42 |
RCS, MoNA, WBS, SR, MW (Joint) |
2007-03-09 09:20 |
Kanagawa |
YRP |
Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa (Keio Univ.) SR2006-90 |
In past time, the research that Viterbi decoder is achieved on VLSI was studied, but it was unique research that Viterbi... [more] |
SR2006-90 pp.9-13 |