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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS)  VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] | VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
| HWS, VLD | 2019-02-27 13:05 |
Okinawa | Okinawa Ken Seinen Kaikan | Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60 |
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] | VLD2018-97 HWS2018-60 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima | Satellite Campus Hiroshima | Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] | RECONF2018-37 pp.15-20 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 11:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68 |
This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] | VLD2017-80 CPSY2017-124 RECONF2017-68 pp.107-112 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] | RECONF2016-45 pp.29-34 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| RECONF | 2011-05-13 11:10 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation and Evaluation of a low power accelerator SLD-2 Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16 |
Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] | RECONF2011-16 pp.91-96 |
| CS, SIP, CAS | 2011-03-03 10:50 |
Okinawa | Ohhamanobumoto memorial hall (Ishigaki)( | A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agric and Tech.) CAS2010-128 SIP2010-144 CS2010-98 |
As multi-processor based computers and electronic devices become the norm, a further emphasis is made on achieving task... [more] |
CAS2010-128 SIP2010-144 CS2010-98 pp.155-160 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:00 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems Tomonori Izumi (Ritsumeikan Univ.) VLD2010-101 CPSY2010-56 RECONF2010-70 |
Reconfigurable logic devices are expected to be key devices to implement real-time, low-power, small autonomous recognit... [more] | VLD2010-101 CPSY2010-56 RECONF2010-70 pp.123-126 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
| RECONF | 2010-09-17 09:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | COGRE: A Novel Compact Logic Cell Architecture for Area Reduction Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-31 |
In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) a... [more] | RECONF2010-31 pp.79-84 |
| ED, SDM | 2010-02-23 11:00 |
Okinawa | Okinawaken-Seinen-Kaikan | Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network Yuta Shiratori, Kensuke Miura (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST) ED2009-208 SDM2009-205 |
We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon’s expansion of Boolean logic functio... [more] | ED2009-208 SDM2009-205 pp.71-76 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:10 |
Kanagawa | A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
|
| CPSY | 2008-12-18 13:15 |
Kyoto | KYOTO Research Park | [Special Invited Talk]
An Introduction of Our Recent Research on VLIW from 3way to 9Nway Yasuhiko Nakashima (NAIST) CPSY2008-48 |
The first VLIW revealed as a hardware structure that could directly execute horizontal micro codes has been raised to on... [more] | CPSY2008-48 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:40 |
Fukuoka | Kitakyushu Science and Research Park | Coarse-Grained Reconfigurable Architecture with Flexible Reliability Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2008-73 DC2008-41 |
Acceptable soft error rate on a VLSI chip varies depending on applications and operating environment so that recent VLSI... [more] | VLD2008-73 DC2008-41 pp.79-84 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka | Kitakyushu Science and Research Park | A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-42 pp.21-26 |
| RECONF | 2008-09-26 10:30 |
Okayama | Okayama Univ. | Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-33 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | RECONF2008-33 pp.63-68 |
| RECONF | 2008-09-26 11:00 |
Okayama | Okayama Univ. | Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34 |
Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loadi... [more] | RECONF2008-34 pp.69-74 |
| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| RECONF | 2008-05-23 09:00 |
Fukushima | The University of Aizu | Designing And Evaluating Dynamically Reconfigurable Processor with Power Gating Technique Yoshiki Saito (Keio Univ.), Toshiaki Shirai (Shibaura Inst.), Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami (Shibaura Inst.), Hideharu Amano (Keio Univ.) RECONF2008-10 |
A dynamically reconfigurable processor achieves high performance making the best use of high degree of parallelism with ... [more] | RECONF2008-10 pp.55-60 |
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