Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SIS, ITE-BCT |
2023-10-12 16:30 |
Yamaguchi |
HISTORIA UBE (Primary: On-site, Secondary: Online) |
[Tutorial Lecture]
Technical Development of Intrusion Prevention Systems with Reconfigurable Devices Tomoaki Sato (Hokusei Gakuen Univ.) SIS2023-19 |
The frequency of Internet use continues to increase in telework and remote work environments. Concurrently, there has be... [more] |
SIS2023-19 pp.19-24 |
PN |
2023-03-02 11:40 |
Okinawa |
(Primary: On-site, Secondary: Online) |
Distributed DDoS Protection Method in the Core Network with Reconfigurable Device Edge Coordination Tomoki Naoi, Masaki Murakami, Yoshihiko Uematsu, Satoru Okamoto, Naoaki Yamanaka (Keidai) PN2022-58 |
Distributed Denial-of-Service (DDoS) attacks are a growing problem today, and it is difficult for individual users to mi... [more] |
PN2022-58 pp.83-89 |
CPSY, DC, IPSJ-ARC [detail] |
2022-07-28 13:30 |
Yamaguchi |
Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] |
CPSY2022-8 DC2022-8 pp.41-46 |
MW |
2022-06-09 15:05 |
Nagano |
Naganoken Nokyo Building (Primary: On-site, Secondary: Online) |
[Invited Talk]
Activites on utilizing Reconfigurable Intelligent Surface for wireless channel control Masashi Iwabuchi, Riku Ohmiya, Tomoaki Ogawa, Yasushi Takatori (NTT) MW2022-26 |
In this talk, we will introduce our activities for wireless channel control using recinfgurable intelligent surface(RIS)... [more] |
MW2022-26 p.19 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online |
Online |
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] |
VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
RECONF |
2020-05-29 10:50 |
Online |
Online |
Proposal of Reconfigurable Device Placement Algorithm Using Placement Quality Judgment Neural Network as Cost Function of SA Method Yuichi Natsume, Tokio Kamada, Kubota Atsushi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2020-13 |
The circuit performance of reconfigurable devices greatly depends on the place-and-route results, so optimal place-and-r... [more] |
RECONF2020-13 pp.71-76 |
PN |
2019-11-14 17:20 |
Kanagawa |
|
Network-based DDoS prevention with newly developed Reconfigurable Communication Processors Naoto Sumita, Masaki Murakami, Yu Nishio, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2019-26 |
In order to cope with traffic growth and service diversity the Photonic Network Processor (PNP) has been proposed. As a ... [more] |
PN2019-26 pp.15-22 |
HWS, VLD |
2019-02-27 13:05 |
Okinawa |
Okinawa Ken Seinen Kaikan |
Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60 |
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] |
VLD2018-97 HWS2018-60 pp.25-30 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima |
Satellite Campus Hiroshima |
Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] |
RECONF2018-37 pp.15-20 |
DC |
2018-02-20 16:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87 |
MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to... [more] |
DC2017-87 pp.61-66 |
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2018-01-19 11:05 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68 |
This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] |
VLD2017-80 CPSY2017-124 RECONF2017-68 pp.107-112 |
MW |
2017-11-10 12:35 |
Okinawa |
Miyakojima Marin Terminal Bldg. |
Direct Parallel Coupling SHF Dual-Band Reconfigurable Bandpass Filter Yuki Kada, Yasushi Yamao (UEC) MW2017-134 |
Recently, the demand for high-speed and high-capacity wireless communication is rapidly increasing. CA (Carrier Aggregat... [more] |
MW2017-134 pp.121-126 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] |
RECONF2016-45 pp.29-34 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] |
VLD2016-54 DC2016-48 pp.61-66 |
MSS |
2016-03-04 11:00 |
Yamaguchi |
KAIKYO MESSE SHIMONOSEKI |
CAME: A Novel Fast Connectivity-Aware MER Enumeration Algorithm for the Online Task Placement on Partially Reconfigurable Device Tieyuan Pan, Lian Zeng (Waseda Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Takahiro Watanabe (Waseda Univ.) MSS2015-82 |
In this paper, we propose a novel fast connectivity-aware Maximal Empty Rectangle(MER) enumeration algorithm for the onl... [more] |
MSS2015-82 pp.79-84 |
RECONF |
2015-06-20 15:50 |
Kyoto |
Kyoto University |
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device Tieyuan Pan, Zhu Li, Lian Zeng, Takahiro Watanabe (Waseda Univ.), Yasuhiro Takashima (Univ. of Kitakyushu) RECONF2015-26 |
Recently, due to the development of technology, the embedded application becomes more and more complex. Consequently, no... [more] |
RECONF2015-26 pp.141-146 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:40 |
Oita |
B-ConPlaza |
Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34 |
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] |
VLD2014-80 DC2014-34 pp.51-56 |
RECONF |
2014-06-12 11:40 |
Miyagi |
Katahira Sakura Hall |
Body bias control of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.) RECONF2014-8 |
For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator cal... [more] |
RECONF2014-8 pp.37-42 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 10:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76 |
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] |
VLD2013-122 CPSY2013-93 RECONF2013-76 pp.119-124 |
RECONF |
2013-05-21 10:35 |
Kochi |
Kochi Prefectural Culture Hall |
Implementation of Speculative Gather System for CMA Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2013-11 |
Cool Mega Array (CMA) is a low power reconfigurable processor array for battery driven mobile devices. A prototype chip ... [more] |
RECONF2013-11 pp.55-60 |