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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 21  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
EMCJ, MW, EST, IEE-EMC [detail] 2019-10-25
16:55
Miyagi Tohoku Gakuin University(Conf. Room 2, Eng. Bldg. 1) A Study of Decoupling Capacitor Implementation by PSD Method Using RBF Interpolation for Meta-modeling
Masashi Kawakami (Akita Prefectural Univ.), Yoshiki Kayano, Fengchao Xiao (UEC), Teruo Tobana (Akita Prefectural Univ.), Yoshio Kami (UEC), Kohei Akimoto, Yoji Isota (Akita Prefectural Univ.) EMCJ2019-70 MW2019-99 EST2019-78
This report newly attempt to propose a multi-objective satisfactory design method, Preference Set-based Design (PSD) to... [more] EMCJ2019-70 MW2019-99 EST2019-78
pp.187-191
EMCJ, IEE-EMC, IEE-MAG 2018-11-22
16:20
Overseas KAIST [Invited Talk] Statistical Eye-diagram Estimation Method Considering Power/Ground Noise Generated by Simultaneous Switching Output Buffers
Youngwoo Kim, Junyong Park, Kyungjun Cho, Joungho Kim (KAIST) EMCJ2018-84
In the high-speed channel, non-linear power/ground noise generated by simultaneous switching buffer outputs (SSOs) noise... [more] EMCJ2018-84
pp.79-80
EMCJ 2018-07-27
13:25
Tokyo Kikai-Shinko-Kaikan Bldg. Analysis of Suppression Mechanism of Power-bus Resonance Using Lossy Resonator Filter with Pi Equivalent Circuits
Sho Kanao, Iokibe Kengo, Yoshitaka Toyota (Okayama Univ.) EMCJ2018-27
Power-bus resonance of printed circuit board causes propagation of electromagnetic noise and detraction of power integri... [more] EMCJ2018-27
pp.31-36
EMCJ, IEE-EMC, IEE-MAG 2017-05-19
11:15
Overseas Nanyang Technological University Power Distribution Network Virtual Prototyping -- A Demonstration of Pre-layout Design, Simulation & Measurement --
Jun Wu Zhang, Eng Kee Chua, Kye Yak See (NTU) EMCJ2017-18
This work presents a demonstration and validation on Power Distribution Network (PDN) ^virtual prototyping ̄ design proce... [more] EMCJ2017-18
pp.63-66
EMCJ, IEE-EMC, IEE-MAG 2017-05-19
13:20
Overseas Nanyang Technological University [Invited Talk] 2.5D Method of Modeling and Simulation for Signal/Power Integrity of High Speed Electronics
En-Xiao Liu, Siping Gao, Hui Min Lee (A*STAR IHPC) EMCJ2017-19
Electromagnetic characteristics related to signal integrity (SI), power integrity (PI) and EMC has become an essential d... [more] EMCJ2017-19
p.67
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
09:15
Kagoshima   Co-design for reducing power supply noises with On-die PDN Impedance
Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86
Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electro... [more] CPM2013-109 ICD2013-86
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
10:30
Fukuoka Centennial Hall Kyushu University School of Medicine A LSI-Package-Board co-evaluation of Power noise in the Digital LSI
Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ.) VLD2012-91 DC2012-57
Problems related with power noise in LSI system are getting prominent
because of the higher integration and lower $V_{d... [more]
VLD2012-91 DC2012-57
pp.183-188
EMT, PN, LQE, OPE, MWP, EST, IEE-EMT [detail] 2012-01-26
09:55
Osaka Osaka Univ. Convention Center Measurement of IC Package Inductance with Transmission Line Embedded in Package
Kengo Iokibe, Ayumi Tanimichi, Yoshitaka Toyota (Okayama Univ.) PN2011-35 OPE2011-151 LQE2011-137 EST2011-85 MWP2011-53
It is of importance for designers to possess accurate inductances of IC packages in power integrity (PI) and electromagn... [more] PN2011-35 OPE2011-151 LQE2011-137 EST2011-85 MWP2011-53
pp.11-16
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
09:25
Miyazaki NewWelCity Miyazaki Measurements and Co-Simulation of On-Chip and On-Boad AC Power Noise in Digital Integrated Circuits
Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ./CREST,JST) CPM2011-163 ICD2011-95
Power noise of an integrated circuit (IC) chip is dominantly characterized by the frequency-domain impedance of a chip-p... [more] CPM2011-163 ICD2011-95
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
10:40
Fukuoka Kyushu University Evaluation of frequency components of power noise in CMOS digital LSI
Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST) CPM2010-124 ICD2010-83
Recent trends of electric devices are higher performance and/or lower power consumption.
To achieve these designs, LSI ... [more]
CPM2010-124 ICD2010-83
pp.1-6
CAS
(2nd)
2010-10-06
11:45
Chiba Makuhari Messe [Invited Talk] PI/SI/EMI simulation technology for high-speed electronic design
Hideki Asai (Shizuoka Univ.)
A variety of noise problems, such as signal integrity, power integrity and electromagnetic interference have become very... [more]
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
16:00
Kochi Kochi City Culture-Plaza [Panel Discussion] EMC Circuit Design and Jisso Design for System LSI -- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side --
Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) CPM2009-142 ICD2009-71
Nowadays, a JISSO design is very important to get the target performance out of a system LSI. More specifically, co-desi... [more] CPM2009-142 ICD2009-71
pp.47-49
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
10:20
Kochi Kochi City Culture-Plaza A Target Imedance of Power Distribution Network and LSI Packaging Design
Narimasa Takahashi, Yoshiyuki Kosaka, Masatoshi Ishii (IBM Japan), Makoto Shiroshita (KYOCERA SLC) CPM2009-144 ICD2009-73
This paper describes the modeling analysis for a power distribution network and demonstrate co-design and co-simulation... [more] CPM2009-144 ICD2009-73
pp.57-62
EMCJ 2009-11-20
13:55
Tokyo Aoyama Gakuin Univ. (Aoyama Campus) Measurement Techniques for On-chip Power Supply Noise Waveforms based on Delay Observation in Inverter Chain Circuits
Yutaka Uematsu, Hideki Osaka, Eiichi Suzuki, Masayoshi Yagyu, Tatsuya Saito (Hitachi Co Ltd.) EMCJ2009-83
To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a
technique for measu... [more]
EMCJ2009-83
pp.25-30
EMCJ, MW, IEE-MAG 2009-10-23
13:20
Iwate Iwate Univ. Application of IC Macro Model (LECCS) to Bypass Circuit Design for Improving EMI/PI Performance
Norimasa Oka, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga (Okayama Univ.) EMCJ2009-68 MW2009-117
An IC macro model for power current analysis, called linear equivalent circuit and current source (LECCS) model, is appl... [more] EMCJ2009-68 MW2009-117
pp.141-146
EMCJ 2008-12-19
11:15
Gifu Gifu Univ. Compatibility Design of EMI Reduction and Power Integrity by Power Decoupling and Destributed Locating of Capacitors in LSI Power Distribution Network
Hiroshi Tanaka, Osami Wada, Takashi Hisakado (Kyoto Univ.) EMCJ2008-91
Conventionally a strategy of reducing impedance of DC power distribution network (PDN) for LSI has been adopted to impro... [more] EMCJ2008-91
pp.31-36
VLD, IPSJ-SLDM 2008-05-09
10:00
Hyogo Kobe Univ. [Invited Talk] NoizeProblems in LSI Design:Challenges and Approaches
Makoto Nagata (Kobe Univ.)
Digital designs intending high-speed and low-power consumption necessarily deal with dynamic power supply noise, for suc... [more] VLD2008-7
pp.1-6
CPM, ICD 2008-01-17
11:10
Tokyo Kikai-Shinko-Kaikan Bldg Design of an On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) CPM2007-132 ICD2007-143
An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The ... [more] CPM2007-132 ICD2007-143
pp.23-27
CPM, ICD 2008-01-18
11:10
Tokyo Kikai-Shinko-Kaikan Bldg [Tutorial Lecture] Survey of Analysis Techniques for On-chip Power Distribution Networks
Takashi Sato (Tokyo Tech.) CPM2007-140 ICD2007-151
Primary techniques and recent trends in power distribution network
(PDN) analysis are reviewed in this paper. Quality ... [more]
CPM2007-140 ICD2007-151
pp.71-76
ICD, CPM 2007-01-18
10:15
Tokyo Kika-Shinko-Kaikan Bldg. Measurement of Delay Degradation Due to Power Supply Noise and Delay Variation Estimation with Full-Chip Simulation
Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. Tech.), Takao Onoye (Osaka Univ.)
Power integrity is an crucial design issue in nano-meter technologies because of lowered supply voltage and current incr... [more] CPM2006-132 ICD2006-174
pp.19-23
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