| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD [detail] | 2020-03-04 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (UoA)  VLD2019-103 HWS2019-76 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2019-103 HWS2019-76 pp.53-58 |
| VLD, HWS (Joint) |
2018-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2017-107 pp.109-114 |
| VLD | 2017-03-01 14:50 |
Okinawa | Okinawa Seinen Kaikan | Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104 |
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] | VLD2016-104 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 09:00 |
Aomori | A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-54 ICD2013-78 IE2013-54 |
As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection ... [more] |
VLD2013-54 ICD2013-78 IE2013-54 pp.41-46 |
|
| VLD | 2013-03-04 14:40 |
Okinawa | Okinawa Seinen Kaikan | Self-Compensation of Manufacturing Variability using On-Chip Sensors Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2012-138 |
Manufacturing variability is becoming more influential on circuit performance and parametric yield, and is predicted to ... [more] | VLD2012-138 pp.13-17 |
| DC | 2011-02-14 16:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2010-69 |
In this study we evaluate the effectiveness of a reconfigurable on-chip debug circuit, in terms of hardware overhead and... [more] | DC2010-69 pp.63-68 |
| ICD | 2008-12-12 16:35 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128 |
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] | ICD2008-128 pp.137-142 |
| ICD, SDM | 2008-07-17 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Co-design of CNT based devices and circuitry
-- How can CNT-based circuit overcome Si-CMOS? -- Shinobu Fujita (Toshiba RDC) SDM2008-138 ICD2008-48 |
Emerging devices using new materials (post-Si) are expected to replace Si-based MOSFET in future. This paper firstly cla... [more] | SDM2008-138 ICD2008-48 pp.59-64 |
| CAS | 2008-02-01 09:25 |
Okinawa | A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-95 |
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. Des... [more] | CAS2007-95 pp.7-12 |
|
[Return to Top Page]