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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EID, ITE-IDY, IEE-EDD, SID-JC, IEIJ-SSL [detail] | 2024-01-26 09:25 |
Kyoto | (Primary: On-site, Secondary: Online) |
Design for micro-LED driving IC Ryoma Matsuno, Zhongzheng Xiao, Rikuto Murayama, Reiji Hattori (Kyushu Univ.)  EID2023-13 |
Recent developments in microLED display technology focus on a method that equips each pixel with a single microIC. Minia... [more] | EID2023-13 pp.45-48 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU) VLD2022-58 RECONF2022-81 |
The SA method is widely used as a logic device placement method for FPGAs. We have introduced neural networks to the pla... [more] | VLD2022-58 RECONF2022-81 pp.13-18 |
| VLD, HWS [detail] | 2022-03-07 09:10 |
Online | Online | Improved placement-method of standard cells considering parallel routing Takeru Furuyashiki, Kunihiro Fujiyoshi (TUAT) VLD2021-76 HWS2021-53 |
Recently, a minimal fab has been proposed for the purpose of small-quantity production of LSI at low cost and in a short... [more] | VLD2021-76 HWS2021-53 pp.1-6 |
| RECONF | 2019-09-19 14:00 |
Fukuoka | KITAKYUSHU Convention Center | A CNN-based Net Wire Length Prediction Method for FPGA Placement Cost Function Yuki Katsuda, Ryota Watanabe, Qian Zhao, Takaichi Yoshida (Kyutech) RECONF2019-21 |
The placement of an FPGA design is performed using the simulated annealing algorithm with a cost function predicting wir... [more] | RECONF2019-21 pp.3-8 |
| PN | 2019-08-27 09:30 |
Hokkaido | Kanpo-No-Yado Otaru | A Study of Virtualized Elastic Regenerator Placement Method in Translucent Elastic Optical Networks Yu Asano, Takahiro Kodama, Masahiko Jinno (Kagawa Univ.) PN2019-17 |
Virtualized elastic regenerative (VER) consists of multiple sub-regenerators and functions as a virtual regenerative rep... [more] | PN2019-17 pp.43-50 |
| CQ (2nd) |
2017-01-21 12:30 |
Osaka | Osaka University Nakanoshima Center | [Poster Presentation]
Performance Evaluation of Caching and Content-Aware Routing Yusaku Hayamizu, Kouji Hirata, Miki Yamamoto (Kansai Univ.) |
Recently, content distribution traffic of the Internet is rapidly increasing. To deal with it, many content-oriented net... [more] | |
| NS | 2016-01-22 15:30 |
Fukuoka | Content-Oriented Traffic Engineering with Content Caching Yusaku Hayamizu, Kouji Hirata, Miki Yamamoto (Kansai Univ.) NS2015-165 |
Recently, many content-oriented schemes have been proposed for network design which is suitable for services required by... [more] | NS2015-165 pp.109-114 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:00 |
Kagoshima | ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2013-49 |
In this paper, we propose an ILP-based method for simultaneous optimal technology mapping, placement and routing for pro... [more] | RECONF2013-49 pp.57-62 |
|
| SIP, CAS, MSS, VLD | 2013-07-11 18:00 |
Kumamoto | Kumamoto Univ. | SOM Based FPGA Placement Method Considering Wire Segment Length Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 |
A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Al... [more] |
CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 pp.83-88 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | An ILP Formulation of Placement and Routing for PLDs Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) VLD2012-75 DC2012-41 |
In this paper, we formulate the simultaneous technology mapping, placement and routing problem for programmable gate a... [more] |
VLD2012-75 DC2012-41 pp.93-98 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 15:25 |
Kanagawa | Hiyoshi Campus, Keio University | Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(To be available after the conference date) [more] | |
| VLD | 2011-09-27 09:45 |
Fukushima | University of Aizu | Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) VLD2011-47 |
FPGAs realize a target circuit by realizing logic cells by LUTs and connecting wires among the logic cells by switch blo... [more] | VLD2011-47 pp.37-42 |
| RCS, AN, MoNA, SR (Joint) |
2010-03-04 09:20 |
Kanagawa | YRP | Optimal Node Placement and Power Allocation in MIMO Two-Way Multihop Networks Rindranirina Ramamonjison, Jonghyun Lee, Kei Sakaguchi, Kiyomichi Araki (Tokyo Inst. of Tech.) RCS2009-285 |
Highly efficient multihop networks can be realized with MIMO two-way relaying techniques. Recently, power allocation and... [more] | RCS2009-285 pp.155-160 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2010-01-29 13:25 |
Tokyo | T.B.D. | Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator Farhad Mehdipour (Kyushu Univ.), Hiroaki Honda (ISIT), Hiroshi Kataoka, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) ICD2009-111 |
As a solution to gain high performance computation, a large scale reconfigurable data-path (LSRDP) processor is introdu... [more] |
ICD2009-111 pp.99-104 |
| RECONF | 2009-09-17 14:50 |
Tochigi | Utsunomiya Univ. | Low-power oriented clustering and placement tools using routability for FPGAs Shinya Imaizumi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-23 |
Power consumption of Field Programmable Gate Arrays (FPGAs) is larger than Application Specific Integrated Circuits (ASI... [more] | RECONF2009-23 pp.25-30 |
| VLD | 2009-03-12 13:50 |
Okinawa | A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-147 |
An on-chip bus architecture is utilized as a communication architecture of a System-on-a-Chip. It is difficult to incre... [more] |
VLD2008-147 pp.123-128 |
|
| RECONF | 2007-09-21 16:15 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Representing dynamically reconfigurable architectures for placement and routing based on graphs with configuration information Vasutan Tunbunheng, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) RECONF2007-30 |
For developing design environment for various types of Dynamically Reconfigurable Processor Arrays (DRPAs), the GCI (... [more] |
RECONF2007-30 pp.89-94 |
| IN, MoNA (Joint) |
2006-11-17 14:50 |
Kumamoto | On Optimum Device Distribution in ZigBee Sensor Network as a Home Network Kazunori Furuhata, Kohei Yuasa, Shiro Sakata (Chiba Univ.), Ryota Kawamoto, Takumi Emori (Alpha Systems Inc.) IN2006-109 |
This article proposes a new placement algorithm of a coordinator node and router nodes in ZigBee sensor network in case ... [more] | IN2006-109 pp.121-126 |
|
| RECONF | 2005-12-02 09:55 |
Fukuoka | Kitakyushu International Conference Center | Online FPGA Placement under I/O Timing Constraints Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
In recent years, FPGAs are effectively-utilized in various fields. Among them, devices with partial reconfiguration are... [more] |
RECONF2005-73 pp.7-12 |
| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 15:25 |
Yamagata | A Global Routing Problem Generation Method based on Rent's Rule Kazuhide Takatsuji, Yoichi Shiraishi (Gunma Univ.) |
This paper presents a method which generates global routing problems based on Rent's Rule. In the layout synthesis of ... [more] | SIP2004-100 ICD2004-132 IE2004-76 pp.67-72 |
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