| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SCE | 2019-01-23 13:30 |
Tokyo | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ)  SCE2018-30 |
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] | SCE2018-30 pp.29-34 |
|
| SCE | 2017-08-09 14:35 |
Aichi | Nagoya Univ. (Higashiyama Campus) | Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) SCE2017-17 |
We have started development of high-throughput rapid single-flux-quantum (RSFQ) microprocessors with the aim of higher p... [more] | SCE2017-17 pp.37-42 |
| ICD, CPSY | 2016-12-16 14:20 |
Tokyo | Tokyo Institute of Technology | [Invited Talk]
A Data-Driven Processor Realizing Trillion Sensors Universe Hiroaki Nishikawa (Univ. of Tsukuba) ICD2016-96 CPSY2016-102 |
This paper introduces a data-driven processor aiming at realizing Trillion Sensors Universe. Execution control scheme in... [more] | ICD2016-96 CPSY2016-102 pp.139-144 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Fast and Accurate Estimation of Execution Cycles for ARM Architecture Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ) VLD2015-73 DC2015-69 |
(To be available after the conference date) [more] | VLD2015-73 DC2015-69 pp.231-236 |
| SAT | 2015-10-07 09:10 |
Osaka | Osaka University Nakanoshima Center | A system performance study on reducing power consumption of DBF/channelizer for communication satellite Teruaki Orikasa, Amane Miura (NICT), Naoki Kobayashi (NEC Space Technologies), Shinji Senba (AXIS) SAT2015-26 |
We have been researching and developing a digital Beam Former and Digital Channelizer (DBF/channelizer) for communicatio... [more] | SAT2015-26 pp.1-6 |
| WBS, SAT (Joint) |
2015-05-28 13:25 |
Tokyo | Tokyo City Univ. (Setagaya Campus) | A study on reducing power consumption of DBF/channelizer for communication satellite Teruaki Orikasa, Amane Miura (NICT), Naoki Kobayashi (NTS), Shinji Senba (AXIS) SAT2015-2 |
We have been researching and developing the DBF/DC (Digital Beam Former and Digital Channelizer) for communication satel... [more] | SAT2015-2 pp.7-12 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-06 15:40 |
Kagoshima | Development of soft macro processor for embedded system Tomoyuki Sugiyama, Takahiro Sasaki, Toshio Kondo (Mie Univ.) CPSY2014-168 DC2014-94 |
Recently, to achieve high performance, low energy consumption and high reliability is required in embedded systems. But ... [more] | CPSY2014-168 DC2014-94 pp.37-42 |
|
| CPSY | 2014-11-13 15:30 |
Hiroshima | Hiroshima University | A Management Scheme for Pipeline Stage Unification Based on Frequency of Use for Functional Units Yuki Tanaka, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) CPSY2014-60 |
This paper shows a management scheme for Pipeline Stage Unification (PSU) which reduces energy consumption by dynamicall... [more] | CPSY2014-60 pp.37-42 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76 |
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] | VLD2013-122 CPSY2013-93 RECONF2013-76 pp.119-124 |
| DC, CPSY (Joint) |
2013-08-02 17:00 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Design of Variable Stages Pipeline Processor on Superscalar Processor Tomoyuki Nakabayashi, Seiji Miyoshi, Takahiro Sasaki, Toshio Kondo (Mie Univ.) CPSY2013-27 |
This paper designs a high performance and low energy superscalar processor using variable stages pipeline (VSP) techniqu... [more] | CPSY2013-27 pp.103-108 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:50 |
Miyazaki | NewWelCity Miyazaki | Power Estimation of Variable Stages Pipeline Processor Using Power Gating Technique Masaki Tanaka, Takahiro Sasaki, Tomoyuki Nakabayashi, Kazuhiko Ohno, Toshio Kondo (Mie Univ) CPSY2011-45 |
Recently, the increase of an energy consumption of mobile computers caused by performance enhancement becomes one seriou... [more] | CPSY2011-45 pp.15-20 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Review of design methodology for pipelined CPU. Case study: trade-off between pipelined and non-pipelined Little Computer 3 Bui Minh Thanh, Hoang Trang, Ho Trung My (HCMUT) |
The review of design methodology for pipelined CPU is presented in this paper. Thanks to high performance, the piplined ... [more] | |
| SIP, CAS, CS | 2010-03-02 13:45 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima | [Poster Presentation]
Low Power Processor Architecture based on a Dynamic Reconfigurable Scheme in Pipeline Stages Masashi Ohki, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-120 SIP2009-165 CS2009-115 |
A processor architecture which can execute instructions in dynamic reconfigurable pipeline manner is proposed. By help o... [more] | CAS2009-120 SIP2009-165 CS2009-115 pp.237-238 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | Pipelined Multithreading with Clustered Communication on Commodity Multi-Core Processors *Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-26 |
Recently proposed pipelined multithreading (PMT) techniques have shown great applicability to parallelizing general prog... [more] | CPSY2009-26 pp.97-102 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 17:25 |
Kanagawa | A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-108 CPSY2008-70 RECONF2008-72 |
Small area, high performance and high productivity are required for application-specific processors in embedded systems.... [more] | VLD2008-108 CPSY2008-70 RECONF2008-72 pp.99-104 |
|
| PN, NS (Joint) |
2008-12-19 12:05 |
Hyogo | Koube Univ. | Development of 640 Gbit/s/port Optical Packet Switch Prototype Hideaki Furukawa, Naoya Wada, Hiroaki Harai, Naganori Takezawa (NICT), Keiichi Nashimoto (EpiPhotonics Corp.), Tetsuya Miyazaki (NICT) PN2008-41 |
We have developed 160 Gbit/s/port optical packet switch (OPS) prototype with optical label processing and optical buffer... [more] | PN2008-41 pp.53-58 |
| CPSY | 2008-10-31 15:00 |
Hiroshima | Hiroshima City Univ. | Development of Improved Variable Stages Pipeline Architecture and its LSI Design Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ) CPSY2008-34 |
Recently, the increase of the energy consumption of mobile computers caused by performance enhancement becomes one ser... [more] |
CPSY2008-34 pp.29-34 |
| VLD, ICD | 2008-03-07 09:40 |
Okinawa | TiRuRu | Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) VLD2007-157 ICD2007-180 |
A multimedia mobile processor HCgorilla developed for ubiquitous network was built in Java CPU, cipher logic, and floati... [more] | VLD2007-157 ICD2007-180 pp.7-12 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 16:35 |
Fukuoka | Kitakyushu International Conference Center | A low power consumption processor with on-chip control mechanism using pipeline stage unification Katsuya Kimura, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) RECONF2007-42 |
In this paper, we implement and estimate the low power consumption processor which uses Pipeline Stage Unification (PSU)... [more] | RECONF2007-42 pp.37-42 |
| ICD, IPSJ-ARC | 2007-06-01 11:00 |
Kanagawa | Design Techniques of Wave Pipelines Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2007-28 |
In order to improve rather complicated design and testing methods of wave-pipelines, our policy is to cover rough tuning... [more] | ICD2007-28 pp.67-72 |
|
[Return to Top Page]