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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)  VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] | VLD2022-56 RECONF2022-79 pp.1-6 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-24 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Implementing a quantum computer simulator Qulacs on FPGAs Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba) VLD2022-72 RECONF2022-95 |
Quantum computer simulation is indispensable for quantum algorithm research since the results of real quantum computers... [more] |
VLD2022-72 RECONF2022-95 pp.74-79 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 09:20 |
Online | Online | The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 |
We are currently developing a multi-FPGA system, Flow-in-Cloud (FiC) system. FiC directly interconnects multiple middle-... [more] | VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 pp.111-116 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-22 14:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Implementation and Evaluation of a Router on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2019-59 CPSY2019-57 RECONF2019-49 |
The trade-off between power efficiency and performance is important in large-scale computing systems like a datacenter. ... [more] | VLD2019-59 CPSY2019-57 RECONF2019-49 pp.31-36 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-22 14:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Performance Evaluation of Using Multi-Switch on a Multi-FPGA System Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2019-60 CPSY2019-58 RECONF2019-50 |
Flow-in-Cloud(FiC) is a system which consists of multiple middle-range FPGAs connected by high-speed serial links, and i... [more] | VLD2019-60 CPSY2019-58 RECONF2019-50 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | Multi-FPGA implementation of deep learning applications Kazusa Musha, Akram Ben Ahmed (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.) RECONF2018-40 |
FiC (Flow-in-Cloud) -SW is an FPGA-based switch board for deep learning applications. In this paper, we implemented a de... [more] | RECONF2018-40 pp.33-38 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 14:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | CPSY2017-40 |
FiC (Flow-in-Cloud) -SW is an FPGA-based switching node for an energy efficientheterogeneous AI computing system. It is ... [more] | CPSY2017-40 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | A study on automated arithmetic pipeline design on multi-FPGA systems Yusuke Hirai, Katsuki Kyan, Makoto Arakaki (Univ. Ryukyus), Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. Ryukyus) RECONF2014-34 |
Computational fluid dynamics (CFD), a powerful tool for aircraft design and other mechanical designs is a major applica... [more] |
RECONF2014-34 pp.1-6 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | Hardware Expansion Protocol in a Scalable Hardware System Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) VLD2013-107 CPSY2013-78 RECONF2013-61 |
Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available numb... [more] | VLD2013-107 CPSY2013-78 RECONF2013-61 pp.31-36 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 17:45 |
Kanagawa | Hiyoshi Campus, Keio University | A study on module allocation in multi-FPGA systems Yusuke Hirai, Kazuaki Nakazato (Univ. of the Ryukyus), Mohamed Sofian bin Abu Talip, Mishra Dipikarani, Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. of the Ryukyus) VLD2013-118 CPSY2013-89 RECONF2013-72 |
Computational fluid dynamics (CFD), a powerful tool for aircraft design and other mechanical designs is a major applica... [more] |
VLD2013-118 CPSY2013-89 RECONF2013-72 pp.97-102 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 13:20 |
Kanagawa | Hiyoshi Campus, Keio University | A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT) VLD2013-126 CPSY2013-97 RECONF2013-80 |
Recently, a scalable and reconfigurable multi-FPGA system has been proposed which consists of two or more boards, each ... [more] |
VLD2013-126 CPSY2013-97 RECONF2013-80 pp.143-148 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 14:10 |
Kagoshima | A Method and Evaluation of Dynamic Relocation for Shared Multi-FPGA System Yuta Ukon, Takuya Otsuka, Takashi Aoki, Yusuke Sekihara, Akihiko Miyazaki (NTT) VLD2013-100 DC2013-66 |
Recently, it is expected to provide high-load services such as analysis of big data or image processing in a data center... [more] | VLD2013-100 DC2013-66 pp.281-286 |
|
| RECONF | 2010-05-14 13:40 |
Nagasaki | Implementation of Arithmetic Pipeline on FLOPS-2D:Multi-FPGA Platform Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) RECONF2010-16 |
Recently, CFD has been attracted as a useful simulation method for aerocraft components. UPACS, one of the practical CFD... [more] | RECONF2010-16 pp.87-92 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 13:45 |
Kanagawa | Circuit Partition Method with Time-multiplexed I/O Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2008-100 CPSY2008-62 RECONF2008-64 |
We propose a partition method to prototype a large scaled system with time-multiplexed I/Os. Recent prototyping of a lar... [more] | VLD2008-100 CPSY2008-62 RECONF2008-64 pp.51-55 |
|
| CAS, SIP, VLD | 2007-06-22 13:40 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | Optimization of Time-Multiplexed I/O Assignment in Multi-FPGA Systems Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-28 VLD2007-44 SIP2007-58 |
Recently, integrated circuit design size and complexity have been increasing rapidly. FPGA systems are used to verify s... [more] |
CAS2007-28 VLD2007-44 SIP2007-58 pp.55-60 |
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