Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 15:55 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
Max Length and Length Difference Minimization for Set Pair Routing Problem with ILP Shutaro Hara, Kunihiro Fujiyoshi (TUAT) VLD2017-60 DC2017-66 |
Set pair routing is the problem to minimize the maximum difference of paths (length difference) that one to one connecte... [more] |
VLD2017-60 DC2017-66 pp.241-246 |
SR |
2014-10-30 13:00 |
Overseas |
I2R, Singapore |
[Poster Presentation]
Prediction of Next ON/OFF State of Primary System by N-order Markov Chain Ryota Nakanishi, Mai Ohta, Makoto Taromaru (Fukuoka Univ.) SR2014-66 |
In this study, we propose a method that predicts the next ON/OFF state of a primary system (PS) by Nth-order Markov chai... [more] |
SR2014-66 pp.35-36 |
RCS |
2014-10-17 10:45 |
Kanagawa |
Keio Univ. |
Study on decoding complexity reduction of chaos MIMO transmission scheme by applying M-algorithm Eiji Okamoto, Yuma Inaba (NITech) RCS2014-181 |
Chaos multiple-input multiple-output (C-MIMO) scheme is a wireless transmission scheme in which both of encryption and c... [more] |
RCS2014-181 pp.141-146 |
AP, WPT (Joint) |
2014-10-16 14:20 |
Hokkaido |
Hokkaido University, Clark Memorial Student Center |
An Experimental Study on Indoor Electrified Floor Structures Tomomi Fujioka, Tetsuo Endo (Taisei), Yoshiki Suzuki, Naoki Sakai, Takashi Ohira (Toyohashi Univ Tech) WPT2014-44 |
This report experimentally examines the influence of electrified floor structures and building components at the upper/l... [more] |
WPT2014-44 pp.43-46 |
VLD |
2014-03-04 09:15 |
Okinawa |
Okinawa Seinen Kaikan |
An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing Yusaku Yamamoto, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2013-142 |
Recent advances in circuit speed force to realize signal propagation delay accurately.
In PCB routing design,
desired... [more] |
VLD2013-142 pp.49-54 |
VLD, IPSJ-SLDM |
2013-05-16 09:50 |
Fukuoka |
Kitakyushu International Conference Center |
A Longest Path Algorithm for Differential Pair Net Considering Connectivity Koji Yamazaki, Yukihide Kohira (Univ. of Aizu) VLD2013-3 |
In recent years, due to the speedup and miniaturization in LSI systems, PCB routing design uses many differential pair n... [more] |
VLD2013-3 pp.13-18 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki |
NewWelCity Miyazaki |
A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing Yusaku Yamamoto, Atsushi Takahashi (Osaka Univ.) VLD2011-87 DC2011-63 |
Recent advances in circuit speed forces to realize signal propagation delay accurately.
In PCB routing design,
desire... [more] |
VLD2011-87 DC2011-63 pp.203-208 |
AN, USN, SR, RCS (Joint) |
2010-10-29 14:40 |
Osaka |
Osaka University |
Study of OFDM Transmission System with Adaptive Guard Interval Control Method Yuya Inagake, Katsuhiro Naito, Kazuo Mori, Hideo Kobayashi (Mie Univ.) RCS2010-139 |
OFDM technique has been received considerable attentions in the wireless communications systems by its robustness agains... [more] |
RCS2010-139 pp.205-210 |
VLD |
2009-03-11 16:40 |
Okinawa |
|
A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-136 |
Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity in... [more] |
VLD2008-136 pp.59-64 |
CAS |
2008-02-01 10:30 |
Okinawa |
|
A note of an estimation of the maximum wire length in the area with obstacle Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-97 |
According to the speeding up of VLSI, the requirement to signal is becoming tighter in order to prevent timing errors. T... [more] |
CAS2007-97 pp.19-23 |