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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2023-02-28 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU)  DC2022-89 |
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrat... [more] | DC2022-89 pp.39-44 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 09:45 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Enrei Jo, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayosi Yoshimura (KSU) CPSY2022-1 DC2022-1 |
In recent years, with the low power design of VLSIs, many low power oriented don't care (X) identification methods and X... [more] | CPSY2022-1 DC2022-1 pp.1-6 |
| DC | 2020-02-26 14:10 |
Tokyo | A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2019-92 |
Recently, in at-speed scan testing, excessive capture power dissipation is a serious problem. Low capture power test gen... [more] | DC2019-92 pp.37-42 |
|
| DC | 2019-02-27 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Capture Power Oriented X-Identification Method Mimicking Fault Propagation Paths of Capture Safe Test Vectors Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ) DC2018-73 |
Low power oriented don't care (X) identification and X filling methods have been proposed to reduce the numbers of captu... [more] | DC2018-73 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:55 |
Hiroshima | Satellite Campus Hiroshima | On the Generation of Random Capture Safe Test Vectors Using Neural Networks Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) VLD2018-51 DC2018-37 |
Excessive capture power consumption at scan testing causes the excessive IR drop and it might cause test-induced yield l... [more] | VLD2018-51 DC2018-37 pp.89-94 |
| DC | 2017-02-21 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A dynamic test compaction method on low power oriented test generation using capture safe test vectors Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ.) DC2016-74 |
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] | DC2016-74 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Design of low power AFE circuit supporting IR array sensor for human detection Shota Ueguchi (Ritsumeikan Univ.), Toshio Kumamoto (Osaka Sangyo Univ.), Masayoshi Shirahata, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2015-129 ICD2015-54 |
We are developing the technology of human monitoring camera systems using intermittent-sensing scheme. In this system, t... [more] | CPM2015-129 ICD2015-54 pp.11-16 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) VLD2014-98 DC2014-52 |
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] | VLD2014-98 DC2014-52 pp.179-184 |
| DC | 2014-06-20 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A X-Filling Method for Low-Capture-Power Scan Test Generation Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-12 |
In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activ... [more] |
DC2014-12 pp.15-20 |
| DC | 2014-02-10 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89 |
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] | DC2013-89 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Scan-Out Power Reduction Method for Multi-Cycle BIST Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68 |
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] | VLD2012-102 DC2012-68 pp.249-254 |
| DC | 2011-06-24 16:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) DC2011-13 |
In this paper, we present a test vector modification method to reduce launch-to-capture power for LOS scheme. The propos... [more] | DC2011-13 pp.29-34 |
| DC | 2011-02-14 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60 |
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] | DC2010-60 pp.7-12 |
| RECONF | 2010-05-14 14:05 |
Nagasaki | A translational system using dynamic reconfigurable processor Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao, Yoshiki Yamaguchi (Univ. of Tsukuba) RECONF2010-17 |
The demand to capture a wide-angle and high-definition video stream has been risen for systems of surveillance, in-vehic... [more] | RECONF2010-17 pp.93-98 |
|
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26 |
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] | VLD2007-71 DC2007-26 pp.7-12 |
| ICD, CPM | 2007-01-19 13:00 |
Tokyo | Kika-Shinko-Kaikan Bldg. | A Constrained Test Generation Method for Low Power Testing Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T) |
High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] | CPM2006-148 ICD2006-190 pp.109-114 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 09:30 |
Fukuoka | Kitakyushu International Conference Center | On Low Capture Power Test Generation for Scan Testing Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST) |
High switching activity occurs when the response to a test vector is captured by flip-flops during scan testing. This ma... [more] | VLD2005-76 ICD2005-171 DC2005-53 pp.1-6 |
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