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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ)  VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 |
SLM (Scalable Logic Module) is a fine-grained reconfigurable logic developed by Kumamoto University, characterized by it... [more] | VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 pp.215-220 |
| HWS, VLD | 2023-03-02 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC) VLD2022-92 HWS2022-63 |
In this paper, we propose CNFET7, the first open-source cell library for7-nm carbon nanotube field-effect transistor (CN... [more] | VLD2022-92 HWS2022-63 p.110 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 13:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] | CPSY2022-8 DC2022-8 pp.41-46 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 14:25 |
Online | Online | Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits Ryosuke Matsuo, Shin-ichi Minato (Kyoto Univ) VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 |
Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-high-spe... [more] | VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 pp.78-83 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 17:30 |
Online | Online | An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15 |
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] | CPSY2020-15 DC2020-15 pp.93-98 |
| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
Design and Demonstration of a 2-input Multiplexer Using Reversible Quantum-Flux-Parametron Logic Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2019-51 |
Reversible quantum-flux-parametron (RQFP) is a logically and thermodynamically reversible logic gate composed of adiabat... [more] | SCE2019-51 pp.87-90 |
|
| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
Methodology for Automating Data Feedback Circuit Synthesis for a 4- bit Counter in Adiabatic Quantum-Flux-Parametron Logic Ro Saito (YNU), Christopher L. Ayala, Olivia Chen (YNU IAS), Tomoyuki Tanaka, Tomohiro Tamura, Nobuyuki Yoshikawa (YNU) SCE2019-58 |
Adiabatic quantum-flux-parametron (AQFP) logic is one kind of superconducting logic family spotlighted as a technologica... [more] | SCE2019-58 pp.117-119 |
|
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-13 11:20 |
Ehime | Ehime Prefecture Gender Equality Center | A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults Peikun Wang, Amir Masaud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-32 DC2019-56 |
In this paper, we propose a new ATPG-based logic optimization method by removing the redundant multiple faults. In order... [more] | VLD2019-32 DC2019-56 pp.19-22 |
| VLD, IPSJ-SLDM | 2019-05-15 15:25 |
Tokyo | Ookayama Campus, Tokyo Institute of Technology | SRAM-Based Synthesis for Multi-Output Gates Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-4 |
Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation... [more] | VLD2019-4 pp.25-30 |
| VLD, IPSJ-SLDM | 2018-05-16 13:30 |
Fukuoka | Kitakyushu International Conference Center | Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-1 |
documentclass[a4paper,11pt]{jarticle} usepackage{kws} usepackage{amssymb} usepackage{amsmath,array,graphicx} ... [more] |
VLD2018-1 pp.1-5 |
| VLD | 2017-03-01 16:20 |
Okinawa | Okinawa Seinen Kaikan | Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models Shogo Senba, Hiroshi Saito (UoA) VLD2016-107 |
This paper proposes a transformation tool that generates an asynchronous Register Transfer Level (RTL) model with bundle... [more] | VLD2016-107 pp.31-36 |
| MSS, SS | 2017-01-26 14:30 |
Kyoto | Kyoto Institute of Technology | A Study on Data-based Modeling of Hot-Water Supply System and its Controler Synthesis Tsukasa Saito (Kyoto Univ.), Yoshihiko Susuki (Osaka Prefecture Univ.), Hikaru Hoshino, Takashi Hikihara (Kyoto Univ.) MSS2016-63 SS2016-42 |
This report performs modeling of a hot-water supply system based on data measured in a medical institution for dialysis ... [more] | MSS2016-63 SS2016-42 pp.35-40 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Hardware implementation of PLC Instructions by high level synthesis Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT) RECONF2016-43 |
The hardware implementation of instruction sequence is a method to conceal and to protect the intellectual property. ... [more] |
RECONF2016-43 pp.19-24 |
| MSS, CAS, IPSJ-AL [detail] | 2015-11-20 14:20 |
Kagoshima | Ibusuki CityHall | Program syntesis from execution traces andt its program verification of distributed algorithms Satoshi Yamane (Kanazawa Univ.) CAS2015-50 MSS2015-24 |
Distributed algorithms are executed on distributed systems such as cloud computing and P2P. It is important to verify ... [more] |
CAS2015-50 MSS2015-24 pp.35-40 |
| VLD | 2015-03-04 11:10 |
Okinawa | Okinawa Seinen Kaikan | Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide Jun Kawasaki, Kimiyoshi Usami (S.I.T.) VLD2014-179 |
Silicon on Thin Buried Oxide (SOTB) technology enables us to reduce supply voltage because the Vth variation can be supp... [more] | VLD2014-179 pp.147-152 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | Don't-Care Extension in Logic Synthesis for Error Tolerant Application Tomoya Inaoka, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2014-89 DC2014-43 |
In logic synthesis for error tolerant applications, external observability don’t-cares can be freely enhanced within a g... [more] | VLD2014-89 DC2014-43 pp.123-128 |
| SP, ASJ-H | 2014-10-24 11:10 |
Wakayama | Nanki Shirahama Onsen Hotel Seamore | [Invited Talk]
An analysis-synthesis system, STRAIGHT, and an Auditory Model, AIM:
-- How to Balance the Ecological Validity and Experimental Control -- Minoru Tsuzaki (KCUA) SP2014-89 |
Tools and models are important components to propel research. In this lecture, how the combination between a fine analys... [more] | SP2014-89 pp.77-82 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:00 |
Hokkaido | Hokkaido University | Accelerating Boolean Matching of LUT-based Circuits using CEGAR method Yusuke Matsunaga (Kyushu Univ.) CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 |
This paper describes an accelerating technique for Boolean matching of LUT-based circuits, which is based on CEGAR (coun... [more] | CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 pp.201-206 |
| CPSY, DC | 2014-04-25 14:00 |
Tokyo | Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2 |
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] | CPSY2014-2 DC2014-2 pp.3-8 |
|
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 13:45 |
Kanagawa | Hiyoshi Campus, Keio University | On Boolean Matching of LUT-based Circuits Yusuke Matsunaga (Kyushu Univ.) VLD2013-127 CPSY2013-98 RECONF2013-81 |
This paper describes two speed-up techniques for Boolean matching of LUT-based circuits. One is one-hot encoding tec... [more] |
VLD2013-127 CPSY2013-98 RECONF2013-81 pp.149-154 |
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