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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EID, ITE-IDY, IEE-EDD, SID-JC, IEIJ-SSL [detail] | 2024-01-26 09:25 |
Kyoto | (Primary: On-site, Secondary: Online) |
Design for micro-LED driving IC Ryoma Matsuno, Zhongzheng Xiao, Rikuto Murayama, Reiji Hattori (Kyushu Univ.)  EID2023-13 |
Recent developments in microLED display technology focus on a method that equips each pixel with a single microIC. Minia... [more] | EID2023-13 pp.45-48 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 15:10 |
Online | Online | An Improved Method of Layout Pattern Classification with Creating Representative Clip Tomoya Masutani, Ishino Shuhei, Kunihiro Fujiyoshi (TUAT) VLD2021-44 ICD2021-54 DC2021-50 RECONF2021-52 |
Layout of VLSI is designed according to design rules, however, hotspots may remain due to feature size shrinking. Recent... [more] | VLD2021-44 ICD2021-54 DC2021-50 RECONF2021-52 pp.156-161 |
| HWS, VLD [detail] | 2021-03-04 10:45 |
Online | Online | [Special Talk]
Efficient VLSI Layout Data Structures and Algorithms
-- a Brief Tutorial -- Shmuel Wimer (Bar-Ilan University) |
Moore's Law which stopped delivering CMOS device speedup for already a decade is still delivering and will do so for the... [more] | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 09:55 |
Online | Online | Seat Layout Method Considering Physical Distance Using Cell Placement Methods in LSI Yukihide Kohira (Univ. of Aizu) VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53 |
Due to the spread of COVID-19 infection, it is required to secure a physical distance between people. In this paper, the... [more] | VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53 pp.127-131 |
| MIKA (2nd) |
2019-10-04 10:15 |
Hokkaido | Hokkaido Univ. | [Poster Presentation]
Wireless System Planning Method Based on Wireless Environment and User Distribution Toshiro Nakahira, Hirantha Abeysekera, Koichi Ishihara, Takatsune Moriyama, Daisuke Goto, Yasushi Takatori (NTT) |
By using a wireless backhaul or a mesh network between access points and installing access points on drones or robots, i... [more] | |
| HWS, VLD | 2019-02-27 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan | Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework Masataka Aoki, Yukihide Kohira (Univ. of Aizu) VLD2018-102 HWS2018-65 |
In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultane... [more] | VLD2018-102 HWS2018-65 pp.55-60 |
| HWS, VLD | 2019-02-28 11:15 |
Okinawa | Okinawa Ken Seinen Kaikan | Implementation Technology for the Advanced Wafer Manufacturing Processes on Optical Transmission LSIs Susumu Hirano, Hideo Yoshida, Kenya Sugihara, Yoshiaki Konishi, Takashi Sugihara, Yoshihiro Ogawa (Mitsubishi Electric) VLD2018-110 HWS2018-73 |
It is indispensable to use the advanced wafer manufacturing processes to develop LSIs of high-speed optical transmission... [more] | VLD2018-110 HWS2018-73 pp.103-108 |
| VLD, IPSJ-SLDM | 2017-05-10 15:00 |
Fukuoka | Kitakyushu International Conference Center | A Method of Layout Pattern Classification Using Clustering Shuhei Ishino, Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT) VLD2017-2 |
Layout of VLSI circuits is designed according to design rule, however, hotspots may remain due to feature size shrinking... [more] | VLD2017-2 pp.7-12 |
| SC | 2016-11-04 13:20 |
Hyogo | Takigawa Memorial Hall, Kobe Univ. | [Invited Talk]
Introduction of Service Engineering and Implementation in Restaurant Business Nobutada Fujii (Kobe Univ.) SC2016-23 |
New research area, Service Science / Engineering, is at present under vivid discussion to realize servitization of manuf... [more] | SC2016-23 pp.23-28 |
| DC | 2016-06-20 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Relationship between the Number of Fan-Outs and Its Wire-length for a logic gate Taiki Kobayashi, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) DC2016-12 |
Many analysis and algorithms have been proposed to reduce wire-lengths based on Steiner trees for VLSI layout designs. A... [more] | DC2016-12 pp.13-18 |
| KBSE | 2016-03-04 18:30 |
Oita | A Support Method for Designing GUI Consistent with Screen Transition Model Tomoya Akase, Shinpei Ogata, Kozo Okano (Shinshu Univ) KBSE2015-71 |
The proper cooperations between UI designers and function designers is important to enhance usability although the funct... [more] | KBSE2015-71 pp.131-136 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47 |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] | VLD2015-51 DC2015-47 pp.81-86 |
| VLD | 2015-03-02 14:55 |
Okinawa | Okinawa Seinen Kaikan | Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming Masato Ito, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-157 |
This paper proposes a routing algorithm of high routability focusing on symmetrical routing used in analog layout. In a ... [more] | VLD2014-157 pp.25-30 |
| VLD | 2015-03-04 09:15 |
Okinawa | Okinawa Seinen Kaikan | On PLL Layouts Evaluation based on Transistor-array Style Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-175 |
The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that uni... [more] | VLD2014-175 pp.123-128 |
| NS, CS, IN (Joint) |
2013-09-12 14:20 |
Miyagi | Tohoku Univ. Research Institute of Electrical Communication 2gokan | [Tutorial Lecture]
Network Platform for Flexibly-Programmable Advanced Service Composition over Virtualization Network Yoshiaki Yoshida, Masaki Fukushima, Yoshinori Kitatsuji, Atsushi Tagami, Shigehiro Ano (KDDI R&D Labs) NS2013-77 IN2013-64 CS2013-30 |
Network virtualization technology receives much attention to its flexibility and robustness, since it enable to construc... [more] | NS2013-77 IN2013-64 CS2013-30 p.27(NS), p.29(IN), p.5(CS) |
| PRMU | 2013-02-21 10:30 |
Osaka | Topic extraction about 3D constitution for occlusion boundary detection Kazuhiko Murasaki, Kyoko Sudo, Yukinobu Taniguchi (NTT) PRMU2012-132 |
In this paper, we propose a new method to detect occlusion boundaries and estimate depth ordering along them. To tackle ... [more] | PRMU2012-132 pp.13-18 |
|
| CAS | 2013-01-28 13:50 |
Oita | Beppu International Convention Center | On Pairwise Vertex-Disjoint Paths Linking Two Nested Rectangular Boundaries in a Rectilinear Graph Hideto Hanada, Daisuke Takafuji, Satoshi Taoka, Toshimasa Watanabe (Hiroshima Univ.) CAS2012-73 |
In a rectilinear graph, a rectangle is fixed in another rectangle. The region bounded by two nested rectangles is $G$.... [more] |
CAS2012-73 pp.41-45 |
| SS | 2013-01-10 15:15 |
Okinawa | Using SAT Solvers for Solving Control-Instruction Layout Problems in Low-Level Assembly Programming for Malbolge Satoshi Ando, Masahiko Sakai, Toshiki Sakabe, Keiichirou Kusakari, Naoki Nishida (Nagoya Univ.) |
Malbolge is known as one of the most esoteric programming languages. Although it became possible to write programs in M... [more] | SS2012-50 pp.25-30 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 09:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Routability-oriented Common-Centroid Capacitor Array Generation Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2012-89 DC2012-55 |
We address layout generation of on-chip matched capacitors with the high relative accuracy. Unit capacitors are placed i... [more] | VLD2012-89 DC2012-55 pp.171-175 |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 14:30 |
Iwate | Hotel Ruiz | CMOS Op-amp Circuit Synthesis with Geometric Programming Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.) VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78 |
This work presents a 6T SRAM design in nanometer process via geometric programming (GP). We adopt the transistor array (... [more] | VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78 pp.77-82 |
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