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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
16:20
Nagasaki Nagasaki Kinro Fukushi Kaikan Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] VLD2015-51 DC2015-47
pp.81-86
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