Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
IE, ITS, ITE-MMS, ITE-ME, ITE-AIT [detail] |
2023-02-22 14:30 |
Hokkaido |
Hokkaido Univ. |
Image Division Based Interframe Prediction Method with Reduced Frame Memory for Ultra-Low-Latency Video-coding Mai Yamaguchi, Matsumura Tetsuya (Nihon Univ.) |
In this paper, we propose a new inter-frame prediction method for Ultra-Low-Latency Video-coding. The proposed method re... [more] |
|
NS |
2022-04-15 13:00 |
Tokyo |
kikai shinkou kaikan + online (Primary: On-site, Secondary: Online) |
Processing Delay Reduction in Cloud Offloading during Handover Koji Sugisono, Katsuma Miyamoto, Hiroki Kanou, Shinya Kawano (NTT) NS2022-4 |
In cloud offloading, the user entity delegates the heavy-loaded tasks to the allocated server in a cloud with plenty of ... [more] |
NS2022-4 pp.19-24 |
OFT |
2018-05-18 10:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg |
A Study of Solid Type Low Latency Optical Fiber Yuto Sagae, Takashi Matsui, Kyozo Tsujikawa, Kazuhide Nakajima (NTT) OFT2018-2 |
Low latency transmission is required especially in the machine-to-machine (M2M) transmission of today’s optical communic... [more] |
OFT2018-2 pp.5-10 |
RCS, SR, SRW (Joint) |
2017-03-01 10:50 |
Tokyo |
Tokyo Institute of Technology |
A Study on Retransmission method with Reduction of Latency and High Reliability in LTE-A Hiroki Ito, Seiichi Sampei (Osaka Univ.) RCS2016-293 |
This paper proposes a latency reduction scheme for high reliable and low latency transmission scheme for Long Term Evolu... [more] |
RCS2016-293 pp.25-30 |
RCS, RCC, ASN, NS, SR (Joint) |
2016-07-21 10:15 |
Aichi |
|
TCP Throughput Improvement Considering Wireless Access Scheme in LTE-Advanced Uplink
-- Examination of TCP ACK Transmission Methods -- Yoshiaki Ohta, Michinaru Nakamura (FLAB), Yoshihiro Kawasaki, Takayoshi Ode (FUJITSU) RCS2016-105 |
LTE-advanced (LTE-A) Pro is being standardized by 3rd Generation partnership Project (3GPP). On of technical challenges ... [more] |
RCS2016-105 pp.65-70 |
RCS |
2016-04-22 15:25 |
Aomori |
Romantopia, A Landscape of Forest and Stars, Hirosaki City |
Evaluation on Shortened TTI of Latency Reduction for LTE-Advanced Pro Yasuaki Yuda (Panasonic), Tomohumi Takata (PSNRD), Ayako Iwata, Tetsuya Yamamoto, Masayuki Hoshino (Panasonic) RCS2016-23 |
In 3GPP, LTE-Advanced Pro has been investigated in order to enhance LTE/LTE-Advanced to 5G mobile system. Latency Reduct... [more] |
RCS2016-23 pp.129-134 |
PN |
2016-03-08 09:25 |
Okinawa |
Okinawaken Seinenkaikan |
Evaluations of the method of latency reduction based on changing the route of uplink burst transmission for the Photonic Sub-Lambda transport network Kyota Hattori, Masahiro Nakagawa, Toshiya Matsuda, Masaru Katayama, Katsutoshi Koda (NTT) PN2015-116 |
Future metro networks need to become more energy-saving and efficient to control the traffic from access networks, whic... [more] |
PN2015-116 pp.75-80 |
NS, IN (Joint) |
2016-03-03 10:10 |
Miyazaki |
Phoenix Seagaia Resort |
The Effectiveness in a Hop by Hop File Delivery System on a Network Naotaka Yonekawa, Katsunori Yamaoka (Tokyo Tech) IN2015-115 |
In the HBH file delivery scheduling, files are sequentially delivered in descending order of the popularity per file siz... [more] |
IN2015-115 pp.43-48 |
RCS, CCS, SR, SRW (Joint) |
2016-03-04 15:30 |
Tokyo |
Tokyo Institute of Technology |
TCP Throughput Improvement Considering Wireless Access Scheme in LTE-Advanced Uplink Yoshiaki Ohta, Nakamura Michiharu (FLAB), Yoshihiro Kawasaki, Takayoshi Ode (FJ) RCS2015-388 |
In LTE-advanced (LTE-A), which is standardized by 3rd Generation partnership Project (3GPP), the reduction of the commun... [more] |
RCS2015-388 pp.321-326 |
VLD |
2016-03-02 13:50 |
Okinawa |
Okinawa Seinen Kaikan |
Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech) VLD2015-140 |
General synchronous circuits are proposed as having taken the place of complete synchronous circuits and do not necessar... [more] |
VLD2015-140 pp.167-172 |
CS, CQ (Joint) |
2012-04-19 12:20 |
Okinawa |
Ishigakijima |
A Study on Efficiency of the Communication with Erasure Correction Code Shohei Iijima, Koichi Ishibashi (Mitsubishi Electric) CS2012-6 |
For content distribution in digital signage systems and file transfer in high-latency environment, the use of erasure co... [more] |
CS2012-6 pp.29-33 |
VLD |
2012-03-07 14:35 |
Oita |
B-con Plaza |
Performance of the Evaluation of a Variable-Latency-Circuit on FPGA Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141 |
The performance of integrated circuits, which are the base of ICT nowaday,
is always requested to be improved.
In de f... [more] |
VLD2011-141 pp.127-132 |
CAS, NLP |
2011-10-20 14:20 |
Shizuoka |
Shizuoka Univ. |
Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2011-41 NLP2011-68 |
This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a m... [more] |
CAS2011-41 NLP2011-68 pp.49-54 |
SR, RCS, USN, AN (Joint) |
2008-10-22 15:15 |
Okinawa |
Okinawa industry support center |
Attribute-based Relay Control for Reduction of Latency in Duty-cycled Wireless Sensor Networks Noriyuki Hashimoto, Hiroaki Taka, Hideyuki Uehara, Takashi Ohira (Toyohashi Univ. of Tech.) USN2008-44 |
When an asynchronous MAC protocol is used in wireless sensor networks, it is hard for a sender node to know whether the ... [more] |
USN2008-44 pp.33-38 |
ICD |
2006-04-13 10:10 |
Oita |
Oita University |
An 8.4ns Column-Access 1.6Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme Shuichi Kubouchi (Hitachi ULSI), Hiroki Fujisawa, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda (Elpida Memory), Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka (Hitachi ULSI), Masayuki Nakamura (Elpida Memory) |
The column access time of a 512Mb DDR3 SDRAM made by a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through ... [more] |
ICD2006-3 pp.13-18 |