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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS, IN (Joint) |
2018-03-02 10:50 |
Miyazaki | Phoenix Seagaia Resort | An Optimal Routing Algorithm for Interconnection of Heterogeneous Ad Hoc Networks Taichi Miya (Tokyo Tech), Ohshima Kohta (TUMSAT), Yoshiaki Kitaguchi, Katsunori Yamaoka (Tokyo Tech)  IN2017-126 |
An abstraction of protocol differences in ad hoc networks is necessary for general-purpose use. The existing studies us... [more] |
IN2017-126 pp.219-224 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| EMD, LQE, OPE, CPM, R | 2014-08-21 11:35 |
Hokkaido | Otaru Economy Center | Integrated waveguide type membrane DFB lasers by BCB bonding on Si substrate Daisuke Inoue, Jieun Lee, Takuo Hiratani, Yuki Atsuji, Tomohiro Amemiya, Nobuhiko Nishiyama, Shigehisa Arai (Tokyo Inst. of Tech.) R2014-26 EMD2014-31 CPM2014-46 OPE2014-56 LQE2014-30 |
On-chip optical interconnection technology which can replace copper electrical global wiring to optical wiring is expect... [more] | R2014-26 EMD2014-31 CPM2014-46 OPE2014-56 LQE2014-30 pp.17-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 11:40 |
Kagoshima | Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63 |
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd,... [more] |
VLD2013-97 DC2013-63 pp.263-268 |
|
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-61 DC2012-27 |
With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are ... [more] | VLD2012-61 DC2012-27 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-82 DC2012-48 |
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] | VLD2012-82 DC2012-48 pp.135-140 |
| IPSJ-SLDM, VLD | 2012-05-30 14:55 |
Fukuoka | Kitakyushu International Conference Center | Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2 |
HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-... [more] | VLD2012-2 pp.7-12 |
| IN | 2011-04-21 14:00 |
Kagawa | Kagawa University | A proposal of the Twice NAT method for VPN On-demand Interconnection System Takaaki Koyama, Hideki Yamada, Toshiharu Kishi, Kimihiko Fukami, Hideo Kitazume (NTT) IN2011-4 |
This article proposes an efficient method in VPN On-demand Interconnection System by one-time TwiceNAT devices. Now pres... [more] | IN2011-4 pp.19-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:50 |
Fukuoka | Kitakyushu Science and Research Park | Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-44 |
By progress of VLSI technology, "On-Chip-Multiprocessor" which processes in parallel on a wafer has been realized, and a... [more] | RECONF2008-44 pp.33-38 |
| RECONF | 2007-05-18 10:00 |
Ishikawa | Kanazawa Bunka Hall | MuCCRA-D:A Dynamically Reconfigurable Processor with Directly Interconnected PEs Masaru Kato, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2007-12 |
MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a typical i... [more] |
RECONF2007-12 pp.67-72 |
| OCS, OPE, LQE | 2005-11-04 12:05 |
Fukuoka | A Reconfigurable and Scalable Hardware Architecture for a Service Oriented Platform Junichi Higuchi, Youichi Hidaka, Shigeyuki Yanagimachi, Takashi Yoshikawa, Soichiro Araki, Atsushi Iwata, Akira Arutaki (NEC) |
We propose new modular scalable switch architecture which is composed of an optical interconnection stackable modular sy... [more] | OCS2005-64 OPE2005-94 LQE2005-102 pp.37-40 |
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