Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
NS, IN (Joint) |
2024-03-01 14:15 |
Okinawa |
Okinawa Convention Center |
A Study of Power Consumption Reduction by Dynamic Hardware Offload in Virtualized Base Stations Riichiro Nagareda, Chikara Sasaki, Atsushi Tagami (KDDI Research), Tomohiro Otani (KDDI) IN2023-103 |
Sixth-generation (6G) mobile communication systems have been studied to deal with the exponential increase
in mobile tr... [more] |
IN2023-103 pp.225-230 |
VLD, HWS, ICD |
2024-03-01 15:30 |
Okinawa |
(Primary: On-site, Secondary: Online) |
A Pipelined NTT Transformer and its Extension Scheme Designed for the Digital Signature Scheme Crystals-Dilithium Pengfei Sun, Makoto Ikeda (Tokyo Univ.) VLD2023-130 HWS2023-90 ICD2023-119 |
As quantum computing advances, it threatens the security of current encryption algorithms, making Post-Quantum Cryptogra... [more] |
VLD2023-130 HWS2023-90 ICD2023-119 pp.161-166 |
RECONF |
2023-09-14 16:40 |
Tokyo |
Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24 |
Vector processors can load lots of data and perform operations in parallel.
The Vector Register Sharing Mechanism, prop... [more] |
RECONF2023-24 pp.18-19 |
HWS, VLD |
2023-03-01 13:25 |
Okinawa |
(Primary: On-site, Secondary: Online) |
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT) VLD2022-76 HWS2022-47 |
Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vec... [more] |
VLD2022-76 HWS2022-47 pp.19-24 |
HWS, VLD |
2023-03-02 15:20 |
Okinawa |
(Primary: On-site, Secondary: Online) |
Secure Cache System against On-Chip Threats Keisuke Kamahori, Shinya Takamaeda (UTokyo) VLD2022-95 HWS2022-66 |
In this paper, we propose a new threat model for secure processor design that considers on-chip threats.
Also, we desi... [more] |
VLD2022-95 HWS2022-66 pp.113-118 |
AI |
2022-07-04 10:40 |
Hokkaido |
(Primary: On-site, Secondary: Online) |
Deep Learning Side-Channel Attacks for Rolled Architecture of PRINCE and Midori128 Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) AI2022-3 |
With the recent expansion of small autonomous mobile robots such as drones, cyber security for small devices is very imp... [more] |
AI2022-3 pp.13-18 |
RECONF |
2022-06-07 14:50 |
Ibaraki |
CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Vector Register Sharing Mechanism for Hardware Acceleration Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2022-5 |
In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] |
RECONF2022-5 pp.26-31 |
CCS |
2022-03-27 14:50 |
Hokkaido |
RUSUTSU RESORT HOTEL & CONVENTION (Primary: On-site, Secondary: Online) |
Examination of neuromorphic circuit architecture consisting of 3D wiring memory devices Naruki Hagiwara, Yoshiki Amemiya, Ali Emiliano Jose, Tetsuya Asai (Hokkaido Univ.), Megumi Akai-Kasaya (Hokkaido Univ./Osaka Univ.) CCS2021-46 |
Analog neural network circuits using non-volatile analog resistance change memory devices have been developed mainly bas... [more] |
CCS2021-46 pp.60-65 |
CAS, CS |
2022-03-04 13:45 |
Online |
Online |
Evaluation of Trojan Detector for AI Hardware Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) CAS2021-94 CS2021-96 |
In recent years, AI edge computing has been expanding to realize real-time inference by implementing AI models on edge d... [more] |
CAS2021-94 CS2021-96 pp.106-111 |
CAS, CS |
2022-03-04 14:35 |
Online |
Online |
Unrolled Architecture oriented Countermeasure Circuit for Low-power Cryptography Midori128 and its Evaluation Shunsuke Miwa, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) CAS2021-96 CS2021-98 |
The number of IoT devices is growing rapidly, ensuring security in those devices is an important issue. Lightweight bloc... [more] |
CAS2021-96 CS2021-98 pp.118-123 |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-24 10:45 |
Online |
Online |
Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] |
VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
HWS, VLD [detail] |
2021-03-03 14:55 |
Online |
Online |
Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware
implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
HWS, VLD [detail] |
2021-03-04 13:25 |
Online |
Online |
A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) VLD2020-83 HWS2020-58 |
In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The lat... [more] |
VLD2020-83 HWS2020-58 pp.85-90 |
ICSS, IPSJ-SPT |
2021-03-02 16:25 |
Online |
Online |
Security Evaluation of PUF utilizing Unrolled Architecture Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa (Meijo Univ.) ICSS2020-53 |
To improve the security of LSI circuit, physically unclonable functions (PUF) have been attracted attention. The glitch ... [more] |
ICSS2020-53 pp.160-165 |
ICD, HWS [detail] |
2020-10-26 13:00 |
Online |
Online |
Design of Efficient AES Hardware with Immediately Fault Detection Capability Yusuke Yagyu, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2020-31 ICD2020-20 |
This paper presents an efficient AES encryption/decryption hardware architecture
with a fault detection scheme.
The pr... [more] |
HWS2020-31 ICD2020-20 pp.36-41 |
DC |
2020-02-26 12:25 |
Tokyo |
|
Glitch PUF utilizing Unrolled Architecture and its Evaluation Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) DC2019-91 |
The physically unclonable functions (PUFs) have attracted attention as technologies for authentication of large scale in... [more] |
DC2019-91 pp.31-36 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-23 11:50 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61 |
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] |
VLD2019-71 CPSY2019-69 RECONF2019-61 pp.111-115 |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 10:45 |
Ehime |
Ehime Prefecture Gender Equality Center |
VLD2019-38 ICD2019-28 IE2019-34 CPSY2019-41 DC2019-62 RECONF2019-39 |
Introducing AI technology trends that have been attracting attention in recent years and an overview of deep learning, w... [more] |
VLD2019-38 ICD2019-28 IE2019-34 CPSY2019-41 DC2019-62 RECONF2019-39 pp.93-94(VLD), pp.3-4(ICD), pp.3-4(IE), pp.3-4(CPSY), pp.93-94(DC), pp.21-22(RECONF) |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-15 10:45 |
Ehime |
Ehime Prefecture Gender Equality Center |
[Keynote Address]
Co-optimization of hardware architecture and algorithm for energy-efficient CNN inference Daisuke Miyashita (Kioxia) VLD2019-47 ICD2019-36 IE2019-42 CPSY2019-46 DC2019-71 RECONF2019-42 |
(To be available after the conference date) [more] |
VLD2019-47 ICD2019-36 IE2019-42 CPSY2019-46 DC2019-71 RECONF2019-42 p.173(VLD), p.41(ICD), p.41(IE), p.53(CPSY), p.173(DC), p.31(RECONF) |
HWS, ICD [detail] |
2019-11-01 14:15 |
Osaka |
DNP Namba SS Bld. |
A Design of Isogeny-Based Cryptographic Hardware Architecture Using Residue Number System Shuto Funakoshi, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2019-60 ICD2019-21 |
In this paper, we will propose an efficient hardware architecture of isogeny-based cryptography. The proposed architectu... [more] |
HWS2019-60 ICD2019-21 pp.19-24 |