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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.)  VLD2013-122 CPSY2013-93 RECONF2013-76 |
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] | VLD2013-122 CPSY2013-93 RECONF2013-76 pp.119-124 |
| RECONF | 2013-09-18 15:30 |
Ishikawa | Japan Advanced Institute of Science and Technology | An Implementation of High Performance Stream Processing on a Reconfigurable Hardware Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Taro Fujii, Koichiro Furuta (Renesas Electronics), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-21 |
Stream processing is one of the applications that reconfigurable hardware can be highly effective. In this paper, we giv... [more] | RECONF2013-21 pp.7-12 |
| IN | 2013-06-20 14:25 |
Fukui | University of Fukui, Bunkyo Campus, Memorial Academy Hall | Writing Window Join Processor in C Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) IN2013-26 |
In the past, there has always been a wide gap between the skills for designing software and hardware. Now that reconfigu... [more] | IN2013-26 pp.7-12 |
| RECONF | 2013-05-20 16:25 |
Kochi | Kochi Prefectural Culture Hall | Speed-up of Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) RECONF2013-5 |
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increas... [more] | RECONF2013-5 pp.25-30 |
| RECONF | 2012-05-29 16:45 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14 |
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FP... [more] |
RECONF2012-14 pp.77-82 |
| RECONF | 2011-09-27 11:25 |
Aichi | Nagoya Univ. | A proposal of pattern matching techniques using dynamically reconfigurable hardware Masato Nogami, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2011-37 |
The pattern matching of the strings using hardware has the problem that increases circuit size when the number of patter... [more] | RECONF2011-37 pp.87-92 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] | VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |
| RECONF | 2010-09-17 11:00 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Removing context memory from Multi-context Dynamically Reconfigurable Processors Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.) RECONF2010-34 |
Although context memory or configuration cache is a key mechanism for quick dyna mic reconfiguration of multi-context ... [more] |
RECONF2010-34 pp.97-102 |
| RECONF | 2010-05-13 14:55 |
Nagasaki | A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2010-4 |
Recently, since a mobile device is required to provide various functions, a lot of specialized hardware modules must be... [more] |
RECONF2010-4 pp.19-24 |
|
| RECONF | 2009-09-18 09:50 |
Tochigi | Utsunomiya Univ. | Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30 |
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] | RECONF2009-30 pp.67-72 |
| RECONF | 2008-09-25 13:30 |
Okayama | Okayama Univ. | Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2008-24 |
Recently, dynamically reconfigurable hardware has been attracted, the research becomes active, and quantitative evaluati... [more] | RECONF2008-24 pp.7-12 |
| RECONF | 2008-05-23 13:50 |
Fukushima | The University of Aizu | Context Virtualization mechanism for Dynamically Reconfigurable Hardware Kengo Nishino, Takeshi Inuo, Nobuki Kajihara (NEC) RECONF2008-19 |
This paper describes a new hardware mechanism which supports context virtualization to run a task which needs the hardwa... [more] | RECONF2008-19 pp.107-112 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 16:10 |
Fukuoka | Kitakyushu International Conference Center | Power analysis on Dynamic Reconfigurable Processor Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) RECONF2007-41 |
Dynamically Reconfigurable Processors have been expected to improve area and power eciency with the time-multiplexed ex... [more] | RECONF2007-41 pp.31-36 |
| RECONF | 2007-09-21 16:15 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Representing dynamically reconfigurable architectures for placement and routing based on graphs with configuration information Vasutan Tunbunheng, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) RECONF2007-30 |
For developing design environment for various types of Dynamically Reconfigurable Processor Arrays (DRPAs), the GCI (... [more] |
RECONF2007-30 pp.89-94 |
| VLD, IPSJ-SLDM | 2007-05-10 14:55 |
Kyoto | Kyodai Kaikan | A Modeling of Dynamically Reconfigurable Processor using SystemC Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
Recently, dynamically reconfigurable processors (DRPs) based on FPGA technology are proposed. DRPs are implemented on... [more] |
VLD2007-4 pp.19-24 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 16:35 |
Fukuoka | Kitakyushu International Conference Center | A Self-Test of Dynamically Reconfigurable Processors Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
Dynamically Reconfigurable Processor (DRP), which can execute a task with multiple hardware contexts so as to achieve hi... [more] | VLD2006-62 DC2006-49 pp.65-70 |
| RECONF | 2005-11-30 16:35 |
Fukuoka | Kitakyushu International Conference Center | Adaptive Computling on the Dynamically Reconfigurable Processor DRP-1 Shohei Abe, Yohei Hasegawa (Keio Univ.), Takao Toi, Takeshi Inuo (NEC System Devices Research Labs.), Hideharu Amano (Keio Univ.) |
Adaptive computing is one of the power reduction methods to take full advantage of reconfigurable devices. The approach,... [more] | RECONF2005-57 pp.25-30 |
| RECONF | 2005-12-02 09:30 |
Fukuoka | Kitakyushu International Conference Center | Development of a Reconfiguration Management Mechanism for Dynamically Reconfigurable System Takanori Susaki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We have developed a dynamically reconfigurable system, which uses an embedded processor FPGA. In this system, an embedde... [more] | RECONF2005-72 pp.1-6 |
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