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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 57  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
10:25
Kanagawa Hiyoshi Campus, Keio University Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] VLD2013-122 CPSY2013-93 RECONF2013-76
pp.119-124
RECONF 2013-09-18
15:30
Ishikawa Japan Advanced Institute of Science and Technology An Implementation of High Performance Stream Processing on a Reconfigurable Hardware
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Taro Fujii, Koichiro Furuta (Renesas Electronics), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-21
Stream processing is one of the applications that reconfigurable hardware can be highly effective. In this paper, we giv... [more] RECONF2013-21
pp.7-12
IN 2013-06-20
14:25
Fukui University of Fukui, Bunkyo Campus, Memorial Academy Hall Writing Window Join Processor in C
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) IN2013-26
In the past, there has always been a wide gap between the skills for designing software and hardware. Now that reconfigu... [more] IN2013-26
pp.7-12
RECONF 2013-05-20
16:25
Kochi Kochi Prefectural Culture Hall Speed-up of Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) RECONF2013-5
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increas... [more] RECONF2013-5
pp.25-30
RECONF 2012-05-29
10:35
Okinawa Tiruru (Naha Okinawa, Japan) A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array
Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2012-4
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use P... [more] RECONF2012-4
pp.19-24
RECONF 2012-05-29
16:45
Okinawa Tiruru (Naha Okinawa, Japan) Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC.
We have evaluated FP... [more]
RECONF2012-14
pp.77-82
VLD 2012-03-07
13:20
Oita B-con Plaza Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor
Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] VLD2011-138
pp.109-114
SAT 2011-12-13
13:55
Aichi Nagoya University Acquisition and tracking in inter-satellite communication with dynamically reconfigurable optical device
Kaori Nishimaki, Atsushi Okamoto, Yuta Wakayama, Akihisa Tomita (Hokkaido Univ.), Yoshihisa Takayama (NICT) SAT2011-62
We propose an innovative acquisition and tracking system using a dynamically reconfigurable optical device for optical i... [more] SAT2011-62
pp.137-140
ICD, IE, SIP, IPSJ-SLDM [detail] 2011-10-25
13:30
Miyagi Ichinobo(Sendai) FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] SIP2011-73 ICD2011-76 IE2011-72
pp.73-76
RECONF 2011-09-27
11:25
Aichi Nagoya Univ. A proposal of pattern matching techniques using dynamically reconfigurable hardware
Masato Nogami, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2011-37
The pattern matching of the strings using hardware has the problem that increases circuit size when the number of patter... [more] RECONF2011-37
pp.87-92
ICD, IPSJ-ARC 2011-01-21
11:40
Kanagawa Keio University (Hiyoshi Campus) Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor
Yoshitaka Hiramatsu (Hitachi), Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Tohru Nojiri, Kunio Uchiyama (Hitachi)
The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogen... [more] ICD2010-136
pp.57-62
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
14:10
Kanagawa Keio Univ (Hiyoshi Campus) Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61
This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] VLD2010-92 CPSY2010-47 RECONF2010-61
pp.49-54
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
10:55
Kanagawa Keio Univ (Hiyoshi Campus) Feasibility of JHDL for Dynamically Reconfigurable Hardware Design
Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] VLD2010-103 CPSY2010-58 RECONF2010-72
pp.133-138
RECONF 2010-09-16
17:00
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) A Peformance Estimation Method for Dynamically Reconfigurable Architecture in Stream Processing
Fumihiko Hyuga, Takashi Yoshikawa (Toshiba) RECONF2010-28
A peformance estimation method for dynamically reconfigurable architecture in stream processing is presented. The archit... [more] RECONF2010-28
pp.61-66
RECONF 2010-09-17
11:00
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Removing context memory from Multi-context Dynamically Reconfigurable Processors
Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.) RECONF2010-34
Although context memory or configuration cache is a key mechanism for quick dyna
mic
reconfiguration of multi-context ... [more]
RECONF2010-34
pp.97-102
RECONF 2010-05-13
14:55
Nagasaki   A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array
Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2010-4
Recently, since a mobile device is required to provide various functions,
a lot of specialized hardware modules must be... [more]
RECONF2010-4
pp.19-24
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
13:25
Kochi Kochi City Culture-Plaza [Invited Talk] A Project on Dynamically Reconfigurable Processors: MuCCRA -- Design emvironment, Low Power design and 3D wireless interconnect --
Hideharu Amano (Keio Univ.) RECONF2009-51
Dynamically reconfigurable processor project MuCCRA(Multi-Core
Configurable Reconfigurable Architecture) aims to establ... [more]
RECONF2009-51
pp.61-66
RECONF 2009-09-17
16:05
Tochigi Utsunomiya Univ. Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells
Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.) RECONF2009-26
One of benefit of coarse-grained dynamically
reconfigurable processor arrays (DRPAs)
is its low dynamic power consump... [more]
RECONF2009-26
pp.43-48
RECONF 2009-09-18
09:50
Tochigi Utsunomiya Univ. Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2
Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] RECONF2009-30
pp.67-72
MSS 2009-06-03
14:25
Osaka Setsunan University, Osaka Center Model checking of cooperated systems consisting of CPU and DRP
Shota Minami, Shingo Takinai, Satoshi Sekoguchi, Satoshi Yamane (Kanazawa Univ.) CST2009-3
In this paper, we propose formal verification for cooperated systems consisting of CPU and DRP. First, we specify CPU as... [more] CST2009-3
pp.13-18
 Results 1 - 20 of 57  /  [Next]  
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