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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 59  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2022-12-16
13:10
Yamaguchi
(Primary: On-site, Secondary: Online)
On Improving the Accuracy of LSI Small Delay Fault Diagnosis
Shinnosuke Fujita, Stefan Holst, Xiaoqing Wen (Kyutech) DC2022-72
With today's tight timing margins, increasing manufacturing variation, and the development of nanometer technology, timi... [more] DC2022-72
pp.1-6
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
14:45
Kumamoto  
(Primary: On-site, Secondary: Online)
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC
Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70
pp.162-167
DC 2022-03-01
14:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
SAT-based LFSR Seed Generation for Delay Fault BIST
Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] DC2021-74
pp.57-62
DC 2020-12-11
13:00
Hyogo
(Primary: On-site, Secondary: Online)
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method
Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] DC2020-59
pp.1-6
DC 2020-02-26
15:00
Tokyo   Improving Controllability of Signal Transitions in the High Switching Area of LSI
Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] DC2019-94
pp.49-54
EST 2020-01-31
09:30
Oita Beppu International Convention Center Worst Case Analysis of DME Tropospheric Propagation Delay
Atsushi Kezuka, Kambayashi Atsushi, Takayuki Yoshihara, Naoki Fujii (ENRI) EST2019-90
RNP route implementations to busy airports are being planed to support aircraft navigation in EU, Japan and other countr... [more] EST2019-90
pp.59-62
DC 2019-12-20
16:30
Wakayama   Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test
Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] DC2019-85
pp.37-42
IN, NS
(Joint)
2019-03-05
16:20
Okinawa Okinawa Convention Center Evacuation route recommendation system by DTN in disaster area using evacuee attribute
Makoto Misumi, Noriaki Kamiyama (Fukuoka Univ.) NS2018-286
Information on evacuation shelters and evacuation routes are important for evacuees to evacuate safely and promptly when... [more] NS2018-286
pp.533-538
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:00
Hiroshima Satellite Campus Hiroshima Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC.
However, faulty TSVs ... [more]
VLD2018-56 DC2018-42
pp.119-124
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:50
Hiroshima Satellite Campus Hiroshima Study on the Applicability of ATPG Pattern for DFT Circuit
Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] VLD2018-58 DC2018-44
pp.131-136
HWS, ISEC, SITE, ICSS, EMM, IPSJ-CSEC, IPSJ-SPT [detail] 2018-07-26
15:25
Hokkaido Sapporo Convention Center A Study on Systematic Insertion of Hardware Trojan Based on Path Delay
Akira Ito, Rei Ueno, Naofumi Homma, Takafumi Aoki (Tohoku Univ.) ISEC2018-44 SITE2018-36 HWS2018-41 ICSS2018-47 EMM2018-43
This paper presents a non-reversible and analytical method for inserting a path delay hardware Trojan (PDHT). The conven... [more] ISEC2018-44 SITE2018-36 HWS2018-41 ICSS2018-47 EMM2018-43
pp.349-356
DC 2018-02-20
09:30
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Weighted Fault Coverage for Two-Pattern Tests
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2017-77
hrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap... [more] DC2017-77
pp.1-6
DC 2018-02-20
10:35
Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79
TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may ... [more]
DC2017-79
pp.13-18
DC 2017-02-21
14:00
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of Operational Unit Binding on Aging-induced Degradation in High-level Synthesis for Asynchronous Systems
Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2016-78
This paper discusses delay-robustness of a four-phase dual-rail asynchronous system at register transfer level (RTL). A ... [more] DC2016-78
pp.23-28
IA 2017-01-27
16:40
Tokyo Kikai-Shinko-Kaikan Bldg. B3 Kenshu-2 room Extention of Layer-5 for DTN on ZNA, a New Generation Network Architecture
Daiki Mitake, Hiroki Watanabe, Kunitake Kaneko, Fumio Teraoka (Keio Univ.) IA2016-89
Recently, clean slate approach which aims at redesign of the Internet has been popular. As one of clean slate approaches... [more] IA2016-89
pp.61-66
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-30
09:25
Osaka Ritsumeikan University, Osaka Ibaraki Campus Design of TDC Embedded in Scan FFs for Testing Small Delay Faults
Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures.
... [more]
VLD2016-62 DC2016-56
pp.105-110
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
14:10
Nagasaki Nagasaki Kinro Fukushi Kaikan An approach to LFSR/MISR seed generation for delay fault BIST
Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66
In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST.
A widely used conventional way to... [more]
VLD2015-70 DC2015-66
pp.213-218
DC 2015-02-13
15:20
Tokyo Kikai-Shinko-Kaikan Bldg A Method of LFSR Seed Generation for Hierarchical BIST
Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85
A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST).
In BIST, alth... [more]
DC2014-85
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
14:45
Oita B-ConPlaza Investigation of the area reduction of observation part and control part in TSV fault detection circuit
Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] VLD2014-72 DC2014-26
pp.3-8
DC 2014-02-10
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan
Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-80
In recent deep sub-micron (DSM) ICs, it is difficult to detect open and
short defects since they do not behave like co... [more]
DC2013-80
pp.7-12
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