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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EE | 2021-01-25 10:55 |
Online | Online (Zoom) | Aged Deterioration Detection of DC-DC Converter Yasuyuki Koga (NiAS), Yudai Furukawa (Fukuoka University), Kazuhiro Kajiwara, Nobumasa Matsui, Fujio Kurokawa (NiAS), Yoshiyasu Nakashima, Yu Yonezawa (FUJITSU Advanced Technology)  EE2020-27 |
In recent years, information and communication services have continued to develop, and the power supply is one of their ... [more] | EE2020-27 pp.22-26 |
| DC | 2020-12-11 13:00 |
Hyogo | (Primary: On-site, Secondary: Online) |
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59 |
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] | DC2020-59 pp.1-6 |
| DC | 2019-12-20 16:30 |
Wakayama | Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85 |
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] | DC2019-85 pp.37-42 |
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| R | 2019-11-28 16:25 |
Osaka | Central Electric Club | Reliability Methodologies for Degradation Predictions Based on Hierarchical Bayesian Modeling and Machine Learning Toru Kaise, Toyohiko Egami (Univ. of Hyogo) R2019-49 |
Degradation processes are significant for making values of reliability. Particularly, it is known that stochastic model... [more] |
R2019-49 pp.35-38 |
| MSS, CAS, IPSJ-AL [detail] | 2018-11-13 13:50 |
Shizuoka | A Study of Degradation Diagnosis of Lithium-ion Battery Using Neural Networks Masahito Arima, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.) CAS2018-73 MSS2018-49 |
The battery aggregation of lithium-ion battery is studied in order to solve the problem of output fluctuation and time m... [more] | CAS2018-73 MSS2018-49 pp.111-114 |
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| EE | 2018-01-30 13:35 |
Oita | Satellite Campus Oita | Failure Prediction Using Low Stability Phenomenon of Digitally Controlled SMPS by Electrolytic Capacitor ESR Degradation Hiroshi Nakao, Yu Yonezawa, Yoshiyasu Nakashima (Fujitsu LAB), Fujio Kurokawa (NiAS) EE2017-71 |
Electrolytic capacitors are known as one of the highest failure rate components in switching mode power supply SMPS). We... [more] | EE2017-71 pp.165-170 |
| VLD | 2015-03-03 09:40 |
Okinawa | Okinawa Seinen Kaikan | Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-163 |
We analyze the efficiency of the design methodology by using circuit simulations. The design methodology which consider... [more] |
VLD2014-163 pp.61-66 |
| R | 2014-11-20 13:45 |
Osaka | Prediction of performance degradation and lifetime for semiconductor devices using markov chain model Kai Momoda, Koichi Endo, Yoshihiro Midoh, Katsuyoshi Miura, Koji Nakamae (Osaka Univ.) R2014-61 |
We study on a method to predict performance degradation and lifetime of semiconductor devices under the assumption that ... [more] | R2014-61 pp.1-5 |
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| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 14:50 |
Kanagawa | Hiyoshi Campus, Keio University | Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2013-129 CPSY2013-100 RECONF2013-83 |
We propose a prediction model for BTI-induced degradation by measurement data on 65nm-process FPGAs. BTI-induced degrad... [more] |
VLD2013-129 CPSY2013-100 RECONF2013-83 pp.161-166 |
| EMD, R | 2011-02-18 15:00 |
Shizuoka | Shizuoka Univ. (Hamamatsu) | Detection of degradation sign of LSI operation using IDDQ Shunsuke Sakamoto, Masaru Sanada (KUT) R2010-46 EMD2010-147 |
VDD supply current (IDDQ) information has been applied to detect LSI evaluation technology, IDDQ which has high fault de... [more] | R2010-46 EMD2010-147 pp.25-30 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | [Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] | |
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