IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 23  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
NC, MBE
(Joint)
2023-03-15
09:55
Tokyo The Univ. of Electro-Communications
(Primary: On-site, Secondary: Online)
Toward the setting up of a tool for comprehensively extracting anatomical projections from the neuroscience literature
Yuta Ashihara (Nihon Univ/UTokyo/WBAI), Iliya Horiguch (UTokyo), Hiroshi Yamakawa (UTokyo/WBAI) NC2022-109
Brain Reference Architecture(BRA), an approach to developing brain-based software, a functional component diagram (HCD) ... [more] NC2022-109
pp.99-104
NS, IN
(Joint)
2022-03-11
10:10
Online Online A resource allocation method of network and computational resources in edge networks
Shota Akiyoshi (Kyutech), Yuzo Taenaka (NAIST), Kazuya Tsukamoto (Kyutech) NS2021-141
Cross-domain data fusion is becoming a key driver to growth of the numerous and diverse applications in IoT era. We have... [more] NS2021-141
pp.109-114
ICSS 2021-11-29
13:50
Kochi KOCHIJYO HALL
(Primary: On-site, Secondary: Online)
Automation of Security Vulnerability Analysis by Auto-generated DFD
Shun Miyazaki, Junpei Kamimura (NEC) ICSS2021-48
System vulnerabilities can be caused by bugs such as buffer overflow, misconfigurations such as improper permission cont... [more] ICSS2021-48
pp.13-18
NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] 2021-06-28
17:15
Online Online Non-approximate Inference for Collective Graphical Models on Path Graphs via Discrete Difference of Convex Algorithm
Yasunori Akagi, Naoki Marumo, Hideaki Kim, Takeshi Kurashima, Hiroyuki Toda (NTT) NC2021-10 IBISML2021-10
The importance of aggregated count data, which is calculated from the data of multiple individuals, continues to increas... [more] NC2021-10 IBISML2021-10
pp.70-77
IA 2019-11-14
15:30
Tokyo Kwansei Gakuin University, Tokyo Marunouchi Campus (Sapia Tower) [Poster Presentation] A Proposal of a routing method based on cost calculation method considering multiple metrics and its evaluation using OpenFlow networks
Kaoru Ogaki, Chisa Takano, Kaori Maeda (Hiroshima City Univ.) IA2019-28
We previously proposed a routing cost calculation method that considers node characteristics (router transfer capacity a... [more] IA2019-28
pp.27-32
RECONF 2018-09-18
14:50
Fukuoka LINE Fukuoka Cafe Space Data Flow Representation and its Applications to Machine Learning Accelerator
Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] RECONF2018-32
pp.73-78
SS, DC 2017-10-19
16:35
Kochi Kochi City Culture-plaza CUL-PORT SS2017-27 DC2017-26 We present FGyama, a novel dataflow graph representation for extracting high-level semantics from source code. FGyama is... [more] SS2017-27 DC2017-26
pp.37-42
VLD, IPSJ-SLDM 2016-05-11
14:55
Fukuoka Kitakyushu International Conference Center A Note on Scheduling Problem Considering the Radiation Resistance of Registers
Keisuke Inoue (KTC), Mineo Kaneko (JAIST)
This paper discusses a high-level design of an application specific integrated circuit (ASIC) with radiation resistance.... [more]
SS, MSS 2016-01-25
14:25
Ishikawa Shiinoki-Geihin-Kan Specification Mining Technology with Data Flow Visualization
Yukiko Abe, Yuuji Tamaki (TOSHIBA) MSS2015-44 SS2015-53
In software development, developers often need to understand source code of existing software to reuse its assets. Howev... [more] MSS2015-44 SS2015-53
pp.53-57
IN 2015-01-22
13:25
Aichi Nagoya International Center A Framework for Monitoring Quality of Service and Detecting Bottlenecks of Computer Systems Based on Graph-Structured Log
Toshio Ito, Yu Kaneko, Tomonori Maegawa (Toshiba Corp.) IN2014-102
This paper proposes a framework for monitoring and improving quality of service of computer systems. The proposed system... [more] IN2014-102
pp.25-30
ITS, IEE-ITS 2014-03-13
09:20
Kyoto Kyoto Univ. An Investigation on Generic Properties of People Flow Database
Mikio Sasaki (DENSO), Yoshihide Sekimoto (Univ. of Tokyo) ITS2013-69
Recently, many people flow databases are being made and widely used not only domestically but also abroad. Practically, ... [more] ITS2013-69
pp.7-12
VLD 2012-03-06
15:30
Oita B-con Plaza CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis
Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-129
In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the proble... [more] VLD2011-129
pp.55-60
ICD, IE, SIP, IPSJ-SLDM [detail] 2011-10-25
15:55
Miyagi Ichinobo(Sendai) Simultaneous Optimization of a CDFG Structure and a Schedule Based on Super-node Representation
Akira Hirata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-77 ICD2011-80 IE2011-76
In high-level synthesis, control-data flow graphs(CDFGs) are frequently used to describe the behavior of circuits since ... [more] SIP2011-77 ICD2011-80 IE2011-76
pp.101-105
LOIS, IPSJ-DC, IPSJ-FI
(Joint)
2010-03-05
18:25
Okinawa Okinawaken-Seinen-Kaikan Example-Based Interactive Assistance for Data-Flow Scripting
Ken Nakayama, Junko Ichino, Tomonori Hashiyama, Shun'ichi Tano (Univ. of Electro-Comm.) LOIS2009-99
The data-flow-type processing, in which the results are obtained by cascading application of various components, is one ... [more] LOIS2009-99
pp.121-125
ICD, IPSJ-ARC, IPSJ-EMB 2010-01-29
13:25
Tokyo T.B.D. Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator
Farhad Mehdipour (Kyushu Univ.), Hiroaki Honda (ISIT), Hiroshi Kataoka, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) ICD2009-111
As a solution to gain high performance computation, a large scale reconfigurable data-path (LSRDP) processor is
introdu... [more]
ICD2009-111
pp.99-104
SIS, SIP, IPSJ-AVM [detail] 2009-09-24
14:00
Hiroshima   Botanical database system searched by images
Takashi Oyabu, Akira Asano (Hiroshima Univ.) SIP2009-46 SIS2009-21
It is difficult to search the name of a flower by the image of a botanical database system. This paper presents a novel ... [more] SIP2009-46 SIS2009-21
pp.29-33
VLD 2009-09-25
11:30
Osaka Osaka University DFG Mapping for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm
Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi Ltd.) VLD2009-39
Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a r... [more] VLD2009-39
pp.57-62
RECONF 2009-09-18
09:00
Tochigi Utsunomiya Univ. A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation
Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2009-28
Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achie... [more] RECONF2009-28
pp.55-60
DC, CPSY 2009-04-21
13:25
Tokyo Akihabara Satellite Campus, Tokyo Metropolitan Univ. A Security Data-Flow Analysis in the Secure Software Development Environment DFITS
Fukutomo Nakanishi, Ryotaro Hayashi, Hiroyoshi Haruki, Yurie Fujimatsu, Mikio Hashimoto (Toshiba Corp.) CPSY2009-4 DC2009-4
We proposed a development environment DFITS, which helps security programmers to create software against tampering in-me... [more] CPSY2009-4 DC2009-4
pp.19-24
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
15:10
Kanagawa   A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application
Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] VLD2008-121 CPSY2008-83 RECONF2008-85
pp.177-182
 Results 1 - 20 of 23  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan